ATA5756/ATA5757 [DATASHEET]

4702L–RKE–03/14

8

4.2

Transmission with ENABLE = High

4.2.1

FSK Mode

switched to external clocking. After typically 0.6ms, the CLK driver is activated automatically (i.e., the microcontroller waits

until the XTO and CLK are ready). After another time period of ≤ 50µs, the PLL is locked and ready to transmit. The power

amplifier is switched on with ASK = H. The Atmel ATA5756/ATA5757 is then ready for FSK modulation. The microcontroller

starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing

the reference frequency of the PLL. IF FSK = L the output frequency is lower, if FSK = H output frequency is higher. After

transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the Atmel

ATA5756/ATA5757 is switched to power-down mode with ENABLE = Low and FSK = Low.

Figure 4-3. Timing FSK Mode with ENABLE Connected to the Microcontroller

4.2.2

ASK Mode

microcontroller is switched to external clocking. After typically 0.6ms, the CLK driver is activated automatically (the

microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 50 µs, the PLL is locked and ready to

transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the

microcontroller returns back to internal clocking. Then, the Atmel ATA5756/ATA5757 is switched to power-down mode with

ENABLE = Low and FSK = Low.

Figure 4-4. Timing ASK Mode with ENABLE Connected to the Microcontroller

ΔT

XTO

> 250µs

FSK

ENABLE

ASK

Power-down

Power-down

Power-up,

PA off

Power-up,

PA on

Power-up,

PA off

CLK

ΔT

XTO

> 250µs

FSK

ENABLE

ASK

Power-down

Power-down

Power-up,

PA off

Power-up,

PA on

(High)

Power-up,

PA off

(Low)

CLK