 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ARM920T Datasheet(PDF) 28 Page - ATMEL Corporation |
|
||||||||||||||||||||||||||||||
ARM920T Datasheet(HTML) 28 Page - ATMEL Corporation |
|
|
28 / 350 page  Programmer’s Model 2-2 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DDI 0151C 2.1 About the programmer’s model The ARM920T processor incorporates the ARM9TDMI integer core, which implements the ARM architecture v4T. It executes the ARM and Thumb instruction sets, and includes EmbeddedICE JTAG software debug features. The programmer’s model of the ARM920T processor consists of the programmer’s model of the ARM9TDMI core (see About the ARM9TDMI programmer’s model on page 2-3) with the following additions and modifications: • The ARM920T processor incorporates two coprocessors: — CP14, which allows software access to the debug communications channel. You can access the registers defined in CP14 using MCR and MRC instructions. These are described in Debug communications channel on page 9-64. — The system control coprocessor, CP15, which provides additional registers that are used to configure and control the caches, MMU, protection system, the clocking mode, and other system options of the ARM920T, such as big or little-endian operation. You can access the registers defined in CP15 using MCR and MRC instructions. These are described in CP15 register map summary on page 2-5. • The ARM920T processor also features an external coprocessor interface that allows the attachment of a closely-coupled coprocessor on the same chip, for example, a floating-point unit. You can access registers and operations provided by any coprocessors attached to the external coprocessor interface using appropriate coprocessor instructions. • Memory accesses for instruction fetches and data loads and stores can be cached or buffered. Cache and write buffer configuration and operation is described in detail in Chapter 4 Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM. • The MMU page tables that reside in main memory describe the virtual to physical address mapping, access permissions, and cache and write buffer configuration. These are created by the operating system software and accessed automatically by the ARM920T MMU hardware whenever an access causes a TLB miss. • The ARM920T has a Trace Interface Port that allows the use of Trace hardware and tools for real-time tracing of instructions and data. |
Similar Part No. - ARM920T |
|
Similar Description - ARM920T |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
