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ARM920T Datasheet(PDF) 78 Page - ATMEL Corporation |
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ARM920T Datasheet(HTML) 78 Page - ATMEL Corporation |
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78 / 350 page  Memory Management Unit 3-26 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DDI 0151C The conditions that generate each of the faults are described in: • Alignment fault on page 3-26 • Translation fault on page 3-26 • Domain fault on page 3-26 • Permission fault on page 3-27. 3.7.1 Alignment fault If alignment fault is enabled (A bit in CP15 register 1 set), the MMU generates an alignment fault on any data word access, if the address is not word-aligned, or on any halfword access, if the address is not halfword-aligned, irrespective of whether the MMU is enabled or not. An alignment fault is not generated on any instruction fetch, nor on any byte access. Note If the access generates an alignment fault, the access sequence aborts without reference to more permission checks. 3.7.2 Translation fault There are two types of translation fault: Section A section translation fault is generated if the level one descriptor is marked as invalid. This happens if bits [1:0] of the descriptor are both 0. Page A page translation fault is generated if the level one descriptor is marked as invalid. This happens if bits [1:0] of the descriptor are both 0. 3.7.3 Domain fault There are two types of domain fault: Section The level one descriptor holds the 4-bit domain field, which selects one of the 16 2-bit domains in the domain access control register. The two bits of the specified domain are then checked for access permissions as described in Table 3-11 on page 3-24. The domain is checked when the level one descriptor is returned. Page The level one descriptor holds the 4-bit domain field, which selects one of the 16 2-bit domains in the domain access control register. The two bits of the specified domain are then checked for access permissions as described in Table 3-11 on page 3-24. The domain is checked when the level one descriptor is returned. |
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