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AT-41511 Datasheet(PDF) 1 Page - Agilent(Hewlett-Packard)

Part No. AT-41511
Description  General Purpose, Low Noise NPN Silicon Bipolar Transistor
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Maker  HP [Agilent(Hewlett-Packard)]
Homepage  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

AT-41511 Datasheet(HTML) 1 Page - Agilent(Hewlett-Packard)

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General Purpose, Low Noise
NPN Silicon Bipolar Transistor
Technical Data
• General Purpose NPN
Bipolar Transistor
• 900 MHz Performance:
AT-41511: 1 dB NF, 15.5 dB GA
AT-41533: 1 dB NF, 14.5 dB GA
• Characterized for 3, 5, and
8 Volt Use
• SOT-23 and SOT-143 SMT
Plastic Packages
• Tape-and-Reel Packaging
Option Available[1]
Hewlett-Packard’s AT-41511 and
AT-41533 are general purpose
NPN bipolar transistors that offer
excellent high frequency
performance at an economical
price. The AT-41533 uses the
3 lead SOT-23, while the AT-415 11
places the same die in the lower
parasitic 4 lead SOT-143. Both
packages are industry standard,
and compatible with high volume
surface mount assembly
The 4 micron emitter-to-emitter
pitch of these transistors yields
high performance products that
can perform a multiplicity of
tasks. The 14 emitter finger
interdigitated geometry yields an
intermediate-sized transistor with
easy to match to impedances, low
noise figure, and moderate
Optimized for best performace
from a 5 to 8 volt bias supply,
these transistors are also good
performers at 2.7 V. Applications
include use in wireless systems as
an LNA, gain stage, buffer,
oscillator, or active mixer.
An optimum noise match near
50 ohms at 900 MHz makes these
devices particularly easy to use as
LNAs. Typical amplifier designs
at 900 MHz yield 1 dB noise
figures with 15 dB or more
associated gain at a 5 V, 5 mA
bias, with good gain and noise
figure obtainable at biases as low
as 2 mA.
The AT-415 series bipolar
transistors are fabricated using
Hewlett-Packard’s 10 GHz fT Self-
Aligned-Transistor (SAT) process.
The die are nitride passivated for
surface protection. Excellent
device uniformity, performance
and reliability are produced by
the use of ion-implantation, self-
alignment techniques, and gold
metalization in the fabrication of
these devices.
1. Refer to “Tape-and-Reel Packaging for
Semiconductor Devices.”
SOT 23 (AT-41533)
SOT 143 (AT-41511)
Outline Drawing

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