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HI-8783 Datasheet(PDF) 2 Page - Holt Integrated Circuits

Part No. HI-8783
Description  ARINC INTERFACE DEVICE 8-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT
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Maker  HOLTIC [Holt Integrated Circuits]
Homepage  http://www.holtic.com
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HI-8783 Datasheet(HTML) 2 Page - Holt Integrated Circuits

   
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HI-8783, HI-8784, HI-8785
PIN DESCRIPTIONS
The HI-8783 isa parallel to serial converter, which when
loaded with four eight bit parallel bytes, outputs the data as
a 32 bit serial word. Timing circuitry insertsa4 bit gap at the
end of each 32 bit word. An input buffer register allows load
operations to take place while the previously loaded word
is being transmitted.
If the PARITY ENB pin is high, the 32nd bit will bea parity
bit, inserted so as to make the 32 bit word have odd parity. If
the PARITY ENB pin is low, the 32nd bit will be the D7 bit of
the 4th byte.
Outputs are provided for both ARINC 429/575 (DATA ONE
and DATA ZERO pins), and ARINC 561 (561 DATA and
561 SYNC pins) type data.
A low signal applied to the
pin resets the HI-8783’s
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loaded into the transmitter.
RESET
FUNCTIONAL DESCRIPTION
PIN
PIN
PIN
SYMBOL
FUNCTION
DESCRIPTION
HI-8783 HI-8783
HI-8784
(20-pin) (22-pin)
HI-8785
21
2
561 SYNC
digital output
ARINC 561 Sync signal
3-10
2-8,10
3-9,11
Dn
digital inputs
Parallel8 bit Data Input
11
11
12
GND
power supply Ground
12
12
13
A0
digital input
Byte address, A0=1 for 1st byte, A0=0 for 2nd, 3rd& 4th bytes
-
-
14
SLP1.5
digital input
Selects the slope of the line driver. High= 1.5us
13
14
15
digital input
Write strobe, loads data on rising edge
14
15
16
digital input
Registers and sequencing logic initialized when low
15
16
17
XMIT CLK
digital input
Clock input for the transmitter
16
17
18
XMT RDY
digital output
Goes high if the buffer register is empty
17
18
19
PARITY ENB digital input
When high the 32nd bit output is odd parity
-
-
20
V-
power supply -10 volt rail
18
19
-
DATA ONE
digital output
Goes high for each ARINC bit output that isa “one”
19
20
-
DATA ZERO digital output
Goes high for each ARINC bit output that isa “zero”
-
-
21
TXAOUT
analog output Line driver ouptut-A side
-
-
22
TXBOUT
analog output Line driver output-B side
20
21
23
561 DATA
digital output
Serial output for ARINC 561 data
-
-
24
V+
power supply +10 volt rail
1
22
1
VCC
power supply +5 volt rail,
WRITE
RESET
Input data can be loaded when the XMT RDY signal is
high, which indicates the input buffer register is empty. The
first8 bit byte is the label byte and is loaded with the A0 in-
put high, which initializes the internal byte counter. The re-
maining three bytes are loaded with A0 in the low state.
Each8 bit byte is loaded into the input buffer register by a
low pulse on the
input. (See figure 1). After the
fourth byte is loaded, the XMT RDY output goes low. The
contents of the input buffer register are transferred to the
output register during the fourth bit period of the gap. If the
fourth gap bit period of the previous word has already been
transmitted, the contents of the input buffer register will be
transferred to the output shift register during the first bit pe-
riod after the loading of the fourth byte, and the XMT RDY
output goes high.
After the output shift register is loaded, the data is shifted
out to the output logic in the order shown in figure 2.
WRITE
The 561 SYNC output pulses low when the XMT CLK is low
during the 8th bit of the ARINC transmission.
The XMIT CLK is the same as the data rate.
HOLT INTEGRATED CIRCUITS
2


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