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HI-8685 Datasheet(PDF) 4 Page - Holt Integrated Circuits

Part No. HI-8685
Description  ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA
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Maker  HOLTIC [Holt Integrated Circuits]
Homepage  http://www.holtic.com
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HI-8685 Datasheet(HTML) 4 Page - Holt Integrated Circuits

 
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HI-8685, HI-8686
Oncea word gap is detected, the data word in the input reg-
ister is transferred to the receive buffer and checked for er-
rors.
When parity detection is enabled (PARITY ENB high), the
received word is checked for odd parity. If there isa parity
error, the 32nd bit of the received data word is set high.
If parity checking is disabled (PARITY ENB low) the 32nd
bit of the data word is always the 32nd ARINC bit received.
The ERROR flag output is set high upon receipt ofa word
gap and the number of bits received since the previous
word gap is less than or greater than 32. The ERROR flag
is reset low when the next valid ARINC word is written into
the receive buffer or when
is pulsed low.
When the data word is transferred to the receive buffer, the
DATA RDY pin goes high. The data word can then be read
in two 16-bit bytes by pulsing the
input low as indi-
cated in Figure 5. The first read cycle resets DATA RDY
low and increments an internal counter to the second
16-bit byte.
The relationship between each bit of an
ARINC word received and each bit of the two 16-bit data
bus bytes is specified in Figure 2.
Whena new ARINC word is received it always overwrites
the receive buffer. If the first byte of the previous word has
not been read, then previous data is lost and the receive
buffer will contain the new ARINC word. However, if the
DATA RDY pin goes high between the reading of the first
and second bytes, the first byte is no longer valid because
the corresponding second byte has been overwritten by
the new ARINC word. Also, the next read will be of the first
byte of the new ARINC word since the internal byte counter
is always reset to the first byte when new data is trans-
ferred to the receive buffer.
ERROR CHECKING
READING RECEIVE BUFFER
RESET
READ
FUNCTIONAL DESCRIPTION (cont.)
TRUTH TABLE 1.
RINA (-10)
RINB (-10)
TESTA
TESTB
RXA
RXB
-1.50V to +1.50V
-1.50V to +1.50V
0
00
0
-3.25V to -6.50V
+3.25V to +6.50V
0
00
1
+3.25V to +6.50V
-3.25V to -6.50V
0
01
0
X
X
0
10
1
X
X
1
01
0
X
X
1
10
0
X= don't care
Read
Byte
Data Bus Bits
ARINC Bits
1st
Byte 1
D0- D15
ARINC1- ARINC 16
2nd
Byte 2
D0- D15
ARINC 17- ARINC 32
FIGURE 2. ORDER OF RECEIVED DATA
RESET
TEST MODE
A low on the
input setsa flip-flop which initializes the
internal logic. When
goes high, the internal logic re-
mains in the initialized state until the first word gap is de-
tected preventing reception ofa partial word.
The built-in differential line receiver can be disabled allowing
the data and clock detection circuitry to be driven directly
with digital signals. The logical OR function of the TESTA
and TESTB is defined in Truth Table 1. The two inputs can
be used for testing the receiver logic and for inputting ARINC
429 type data derived from another source/ protocol. See
Figure4 for typical test input timing.
The device should always be initialized with
imme-
diately after entering the test mode to cleara partial word
that may have been received since the last word gap. Oth-
erwise, an ERROR condition may occur and the first 32 bits
of data on the test inputs may not be properly received.
Also, when entering the test mode, both TESTA and TESTB
should be set high and held in that state for at least one
word gap period (17 gap clocks) after
goes high.
When exiting the test mode, both test inputs should be held
low and the device initialized with
RESET
RESET
RESET
RESET
RESET.
HOLT INTEGRATED CIRCUITS
4


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