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6

©2014 Fairchild Semiconductor Corporation

FDMC86259P Rev.C

Dimensional Outline and Pad Layout

NOTES: UNLESS OTHERWISE SPECIFIED

A) PACKAGE STANDARD REFERENCE:

JEDEC MO-240, ISSUE A, VAR. BA,

DATED OCTOBER 2002.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE BURRS

OR MOLD FLASH. MOLD FLASH OR

BURRS DOES NOT EXCEED 0.10MM.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M-1994.

E) DRAWING FILE NAME: PQFN08HREV1

8

1

5

4

4

1

85

LAND PATTERN

RECOMMENDATION

14

85

PKG

C

L

PKG

L

C

PKG L

C

L

C

SYM

PKG

C

L

A

B

DETAIL A

SCALE: 2X

SEE

DETAIL A

3.40

3.20

3.40

3.20

1.95

0.65

0.37

0.27

(8X)

0.50

0.30

2.05

1.85

0.10 C A B

(0.34)

(2.27)

(0.52 TYP)

0.25

0.15

0.80

0.70

0.10 C

0.08 C

0.05

0.00

C

SEATING

PLANE

2.37 MIN

(0.45)

(0.40)

(0.65)

2.15 MIN

0.70 MIN

0.42 MIN

(8X)

1.95

0.65

PIN 1

INDICATOR

(0.33) TYP

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/PQ/PQFN08H.pdf.