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HD74LVC533 Datasheet(PDF) 1 Page - Hitachi Semiconductor |
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HD74LVC533 Datasheet(HTML) 1 Page - Hitachi Semiconductor |
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HD74LVC533 Octal D-type Transparent Latches with 3-state Outputs ADE-205-070B(Z) Rev.2 September 1995 Description The HD74LVC533 has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • V CC = 2.0 V to 5.5 V • All inputs V IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • Typical V OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical V OH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±24 mA (@V CC = 3.0 V to 5.5 V) Function Table Inputs G LE D Output Q H XXZ LH LH L HHL LLX Q 0 H : High level L : Low level X : Immaterial Z : High impedance Q 0 : Level of Q before the indicated steady input conditions were established. |
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