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HD74HC165 Datasheet(PDF) 1 Page - Hitachi Semiconductor

Part No. HD74HC165
Description  Parallel-load 8-bit Shift Register
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Maker  HITACHI [Hitachi Semiconductor]
Homepage  http://www.renesas.com/eng
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HD74HC165 Datasheet(HTML) 1 Page - Hitachi Semiconductor

   
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HD74HC165
Parallel-load 8-bit Shift Register
Description
This 8-bit serial shift register shifts data from Q
A to QH when clocked.
Parallel inputs to each stage are
enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary
output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with
the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of
the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the
parallel inputs is loaded directly into the register independent of the state of the clock.
Features
• High Speed Operation: t
pd (Clock to QH) = 21 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V
CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I
CC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Parallel
Internal outputs
Output
Shift/Load
Clock Inhibit
Clock
Serial
A ······ H
Q
A
Q
B
Q
H
L
X
X
X
a ······h
a
b
h
HL
L
X
X
Q
A0
Q
B0
Q
H0
HL
HX
H
Q
An
Q
Gn
HL
L
XLQ
An
Q
Gn
HH
X
X
X
Q
A0
Q
B0
Q
H0


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