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HD74CDCV857 Datasheet(PDF) 4 Page - Hitachi Semiconductor

Part No. HD74CDCV857
Description  2.5-V Phase-lock Loop Clock Driver
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Maker  HITACHI [Hitachi Semiconductor]
Homepage  http://www.renesas.com/eng
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HD74CDCV857 Datasheet(HTML) 4 Page - Hitachi Semiconductor

 
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HD74CDCV857
4
Pin Function
Pin name
No.
Type
Description
AGND
17
Ground
Analog ground. AGND provides the ground reference for the
analog circuitry.
AV
CC
16
Power
Analog power supply. AV
CC provides the power reference for
the analog circuitry. In addition, AV
CC can be used to bypass
the PLL for test purposes. When AV
CC is strapped to ground,
PLL is bypassed and CLK is buffered directly to the device
outputs. This bypass mode is used for Hitachi test.
CLK,
CLK
13, 14
I
Differential
input
Clock input. CLK provides the clock signal to be distributed by
the HD74CDCV857 clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed
phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization
time is required for the PLL to phase lock the feedback signal to
its reference signal.
FBIN, FBIN
35, 36
I
Differential
input
Feedback input. FBIN provides the feedback signal to the
internal PLL. FBIN must be hard-wired to FBOUT to complete
the PLL. The integrated PLL synchronizes CLK and FBIN so
that there is nominally zero phase error between CLK and
FBIN.
FBOUT,
FBOUT 32, 33
O
Differential
output
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired
to FBIN, FBOUT completes the feedback loop of the PLL.
PWRDWN
37
I
Output bank enable.
PWRDWN is the output enable for all
outputs. When
PWRDWN is low, VCO will stop and all outputs
are disabled to a high impedance state. When
PWRDWN will
be returned high, PLL will re-synchroniz to CLK frequency and
all outputs are enabled.
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
Ground
V
DDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
Power
Power supply
Y
3, 5, 10, 20,
22, 27, 29,
39, 44, 46
O
Differential
output
Clock outputs. These outputs provide low-skew copies of CLK.
Y
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
O
Differential
output
Clock outputs. These outputs provide low-skew copies of
CLK.


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