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HD74ALVC162834 Datasheet(PDF) 1 Page - Hitachi Semiconductor

Part No. HD74ALVC162834
Description  18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable
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Maker  HITACHI [Hitachi Semiconductor]
Homepage  http://www.renesas.com/eng

HD74ALVC162834 Datasheet(HTML) 1 Page - Hitachi Semiconductor

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18-bit Universal Bus Driver with 3-state Outputs
and Inverted Latch Enable
ADE-205-217D (Z)
5th. Edition
December 1999
The HD74ALVC162834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V
CC operation.
Data flow from A to Y is controlled by the output enable (
OE). The device operates in the transparent mode
when the latch enable (
LE) is low. When LE is low, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If the
LE is high, the A data is stored in the latch/flip flop on the low to high
transition of CLK. When
OE is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE should be tied to V
CC through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
All outputs, which are designed to sink up to 12 mA, include 26
Ω resistors to reduce overshoot and
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• V
CC = 2.3 V to 3.6 V
• Typical V
OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical V
OH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@V
CC = 3.0 V)
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required

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