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HIP6004BCB Datasheet(PDF) 11 Page - Intersil Corporation |
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HIP6004BCB Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 15 page 11 below). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the lower MOSFET’s body diode. The gate-charge losses are dissipated by the HIP6004B and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Standard-gate MOSFETs are normally recommended for use with the HIP6004B. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET’s absolute gate-to- source voltage rating determine whether logic-level MOSFETs are appropriate. Figure 9 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC. The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. Logic-level MOSFETs can only be used if the MOSFET’s absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC. Figure 10 shows the upper gate drive supplied by a direct connection to VCC. This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic- level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC. Schottky Selection Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode’s rated reverse breakdown voltage must be greater than the maximum input voltage. PUPPER = Io 2 x r DS(ON) x D + 1 2 Io x VIN x tSW x FS PLOWER = Io 2 x r DS(ON) x (1 - D) Where: D is the duty cycle = VOUT / VIN, tSW is the switch ON time, and FS is the switching frequency. +12V PGND HIP6004B GND LGATE UGATE PHASE BOOT VCC +5V OR +12V NOTE: NOTE: VG-S ≈ VCC CBOOT DBOOT Q1 Q2 + - FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION VG-S ≈ VCC -VD D2 + VD - +12V PGND HIP6004B GND LGATE UGATE PHASE BOOT VCC +5V OR LESS NOTE: NOTE: VG-S ≈ VCC Q1 Q2 + - FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION VG-S ≈ VCC -5V D2 HIP6004B |
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