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7005S35JI Datasheet(PDF) 19 Page - Integrated Device Technology |
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7005S35JI Datasheet(HTML) 19 Page - Integrated Device Technology |
19 / 21 page 6.42 IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 19 Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread back rather than a one), the left processor would assume control of the lower4K.Meanwhiletherightprocessorwasattemptingtogaincontrolof theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse to the zero it had attempted to write into Semaphore 0. At this point, the softwarecouldchoosetotryandgaincontrolofthesecond4Ksectionby writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining control,itwouldlockouttheleftside. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo itssemaphorerequestandperformothertasksuntilitwasabletowrite,then readazerointoSemaphore1.Iftherightprocessorperformsasimilartask withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap 4K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- Port RAM or other shared resources into eight parts. Semaphores can evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess theirassignedportionsofmemorycontinuouslywithoutanywaitstates. Semaphoresarealsousefulinapplicationswherenomemory“WAIT” stateisavailableononeorbothsides.Onceasemaphorehandshakehas been performed, both processors can access their assigned RAM segmentsatfullspeed. Another application is in the area of complex data structures. In this case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor mayberesponsibleforbuildingandupdatingadatastructure.Theother processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting processorreadsanincompletedatastructure,amajorerrorconditionmay exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks itandthenisabletogoinandupdatethedatastructure.Whentheupdate is completed, the data structure block is released. This allows the interpretingprocessortocomebackandreadthecompletedatastructure, therebyguaranteeingaconsistentdatastructure. Figure 4. IDT7005 Semaphore Logic D0 2738 drw 20 D Q WRITE D0 D Q WRITE SEMAPHORE REQUEST FLIP FLOP SEMAPHORE REQUEST FLIP FLOP LPORT RPORT SEMAPHORE READ SEMAPHORE READ , |
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