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ML22823 Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers |
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ML22823 Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 63 page FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 5/63 PIN DESCRIPTION (COMMON TO ALL PRODUCTS) Pin Symbol I/O Initial value (*1) Description 1 AIN I 0 Input pin for speaker amplifier. 2 TESTI0 I 0 Input pin for testing. Fix this pin to “L” level (DGND level). This pin has a pull-down resistor built in. 3 RESETB I 0 (*2) Input pin for reset. At the “L” level, the LSI enters initial state. During reset, the entire circuitry stops and enters power down state. Input “L” level when power is supplied. After the power supply voltage is stable, drive this pin to “H” level. Then the entire circuitry can be powered up. This pin has a pull-up resistor built in. 4 TESTO O Hi-Z Output pins for testing. Leave these pins open. 6, 7 SEL0 SEL1 I 0 Memory bank switching pins. Fix these pins to “L” level when the memory bank function is not used. 8, 14, 19, 26 DGND — — Digital ground pin. Also serves as a ground pin for the internal memory. 13 CBUSYB O 1 Output pin for command processing status. This pin outputs “L” level during command processing. Any command should be entered when this pin is “H” level. 15 XT I 0 Connect to the crystal or ceramic resonator. A feedback resistor around 1 M Ω is built in between this pin and the XTB pin. Use this pin if need to use an external clock. If the resonator is used, connect it as close to this pin as possible. 16 XTB O 1 Connect to the crystal or ceramic resonator. When to use an external clock, leave this pin open. If the resonator is used, connect it as close to this pin as possible. 17, 22 DVDD — — Power supply pins for logic circuitry. Connect a capacitor of 0.1 μF or more between these pins and DGND pins. 18, 20 N.C — — Non connected pins. Leave these pins open. 21 VDDL — 0 Regulator output pin for internal logic circuitry. Connect a capacitor recommended between this pin and DGND pin. 23 VDDR — 0 Regulator output pin for Built-in ROM. Connect a capacitor recommended between this pin and DGND pin. 24 TESTI1 — 0 Test pin. Fix this pin to a DGND level. 25 SG — 0 Reference voltage output pin for the speaker amplifier built-in. Connect a capacitor recommended between this pin and DGND pin. 27 SPVDD — — Power supply pin for the speaker amplifier. Connect a bypass capacitor of 0.1 μF or more between this pin and SPGND pin. 28 SPGND — — Ground pin for the speaker amplifier. 29 SPP O 0 Positive(+) output pin of the speaker amplifier built-in. Serves as the LINE output (*3), if built-in speaker amplifier is not used. 30 SPM O Hi-Z Negative(-) output pin of the speaker amplifier built-in. *1: Indicates the initial value during reset input or power down. *2: “H” during power down. *3: Outputs a voice signal before amplified by the speaker amplifier built-in. |
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