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SAB82525H-V21 Datasheet(PDF) 61 Page - Siemens Semiconductor Group

Part No. SAB82525H-V21
Description  High-Level Serial Communication Controller Extended
Download  126 Pages
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Manufacturer  SIEMENS [Siemens Semiconductor Group]
Direct Link  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

SAB82525H-V21 Datasheet(HTML) 61 Page - Siemens Semiconductor Group

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Semiconductor Group
61
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Since a transmitted zero is given priority over a 1 due to the OR connection at the bus, and
since the individually combined stations in the address field of the transmitted HDLC frame
differ from one another, the fact that a collision has occurred will be detected prior to or at the
latest within the address field. The frame of the transmitter with the highest temporary priority
(address field) is not affected and is transmitted without interruptions. All other transmitters
terminate their operation immediately.
Note: If a wired OR connection has been realized by an external pull-up resistor without decoupling,
the data output (T
×DA/T×DB) can be used as an open drain output and connected directly to
the C
×DA, C×DB input.
Priority Principle
When the HDLC frame has been successfully transmitted by the HSCX, the priority is
decremented. In order to transmit an additional frame, ten successive 1’s must be present on
the bus. This fact is used as a criterion to ensure that the higher priority transmitters do not
contain any transmit requests. It is now possible to transmit a frame and the priority can be
increased again (8 successive 1’s). This method offers a priority allocation based on the
selection of a particular address. It also ensures that each subscriber can access the bus at a
pre-determinable time.
Timing Modes
If a bus configuration has been selected, the HSCX provides two timing modes, differing in the
period between sending data and evaluation of the transmitted data for collision detection.
timing mode 1 (CCR1: SC1, SC0 = 01)
Data is output with the rising edge of the transmit clock via the T
×D pins, and evaluated
1/2 clock period later with the falling clock edge at the C
×D pins.
timing mode 2 (CCR1: SC1, SC0 = 11)
Data is output with the falling clock edge and evaluated with the next falling clock edge.
Thus one complete clock period is available during data output and their evaluation.
Note: If the bus is occupied by other transmitters and/or there is no transmit request in the HSCX, log 1
will be continuously transmitted at the T
×DA/T×DB output.
Bus Access Procedure
The idle state of the bus is identified by eight or more successive 1’s. In case of a transmit re-
quest in the HSCX, the frame is transmitted and the bus is identified as busy with the first zero
of the opening flag (start flag).
After the frame has been transmitted, the bus becomes available again by transmitting 1’s.
Collisions
During the transmitting process, the data transmitted from the HSCX is compared with the data
on the bus. In case an erroneous bit is detected (log 1 sent and log 0 detected, or vice versa)
the frame is immediately aborted, and idle (log 1) is transmitted. Transmission will be initiated
again by the HSCX as soon as possible.


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