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SAB82525H-V21 Datasheet(PDF) 40 Page - Siemens Semiconductor Group |
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SAB82525H-V21 Datasheet(HTML) 40 Page - Siemens Semiconductor Group |
40 / 126 page ![]() Semiconductor Group 40 SAB 82525 SAB 82526 SAF 82525 SAF 82526 Five interrupt indications can be read directly from the ISTA register and another six interrupt indications from the extended interrupt register (EXIR). After the HSCX has requested an interrupt by setting its INT pin to low, the CPU must first read the interrupt status register of channel B (ISTA-B) in the associated interrupt service routine. The three lowest order bits (bit 2-0) of ISTA-B (ICA, EXA, EXB) point are set to those registers in which the actual interrupt source is indicated. It is possible that several interrupt sources are indicated referring to one interrupt request (e.g. if the ICA bit is set, at least one interrupt is indicated in the ISTA register of channel A). An interrupt source from channel B is implicitly indicated by bits 7-3 of ISTA-B; therefore these bits must also always be checked. The INT pin of the HSCX remains active until all interrupt sources are cleared by reading the corresponding interrupt register. Therefore it is possible that the INT pin is still active when the interrupt service routine is finished. For some interrupt controllers or CPUs it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. This can be done by masking all interrupts at the end of the interrupt service routine (writing FFH into the MASK register) and write back the old mask to the MASK register. The HSCX interrupt sources can be logically grouped into – receive interrupts, – transmit interrupts, and – special condition interrupts. Each interrupt indication of the ISTA registers can be selectively masked by setting the respective bit in the MASK register. The following tables give a complete overview of the individual interrupt indications and the cause of their activation as well as specific restrictions (marked with ’’*’’). |
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