DAC8408

–9–

REV. A

Figure 4. Equivalent DAC Circuit (AII Digital Inputs LOW)

DIGITAL SECTION

Figure 5 shows the digital input/output structure for one bit.

The digital WR, WR, and RD controls shown in the figure are

internally generated from the external A/B, R/W, DS1, and DS2

signals. The combination of these signals decide which DAC is

selected. The digital inputs are CMOS inverters, designed such

that TTL input levels (2.4 V and 0.8 V) are converted into

CMOS logic levels. When the digital input is in the region of 1.2 V

to 1.8 V, the input stages operate in their linear region and draw

current from the +5 V supply (see Typical Supply Current vs.

Logic Level curve on page 6). It is recommended that the digital

order to minimize supply currents. This allows maximum sav-

ings in power dissipation inherent with CMOS devices. The

three-state readback digital output drivers (in the active mode)

provide TTL-compatible digital outputs with a fan-out of one

TTL load. The three state digital readback leakage-current is

typically 5 nA.

Figure 5. Digital Input/Output Structure

INTERFACE LOGIC SECTION

DAC Operating Modes

• All DACs in HOLD MODE.

• DAC A, B, C, or D individually selected (WRITE MODE).

• DAC A, B, C, or D individually selected (READ MODE).

• DACs A and C simultaneously selected (WRITE MODE).

• DACs B and D simultaneously selected (WRITE MODE).

DAC Selection: Control inputs, DS1, DS2, and A/B select

which DAC can accept data from the input port (see Mode Se-

lection Table).

Mode Selection: Control inputs DS and R/W control the oper-

ating mode of the selected DAC.

Write Mode: When the control inputs DS and R/W are both

low, the selected DAC is in the write mode. The input data

latches of the selected DAC are transparent, and its analog out-

put responds to activity on the data inputs DB0–DB7.

Hold Mode: The selected DAC latch retains the data that was

present on the bus line just prior to DS or R/W going to a high

state. All analog outputs remain at the values corresponding to

the data in their respective latches.

Read Mode: When DS is low and R/W is high, the selected

DAC is in the read mode, and the data held in the appropriate

latch is put back onto the data bus.

MODE SELECTION TABLE

Control Logic

DS1

DS2

A/B

R/W

Mode

DAC

L

H

H

L

WRITE

A

L

H

L

L

WRITE

B

H

L

H

L

WRITE

C

H

L

L

L

WRITE

D

L

H

H

H

READ

A

L

H

L

H

READ

B

H

L

H

H

READ

C

H

L

L

H

READ

D

L

L

H

L

WRITE

A&C

L

L

L

L

WRITE

B&D

H

H

X

X

HOLD

A/B/C/D

L

L

H

H

HOLD

A/B/C/D

L

L

L

H

HOLD

A/B/C/D

L = Low State, H = High State, X = Irrelevant