ADC12L063 datasheet(7/31 Pages) TI1

Part #	ADC12L063

Description	12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold

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ADC12L063

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SNAS144E – JULY 2001 – REVISED MARCH 2013

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = VDR = +3.3V, PD

= 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other

limits TA = TJ = 25°C

(1) (2) (3)

Units

Symbol

Parameter

Conditions

Typical (4)

Limits (4)

(Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

12

Bits

INL

Integral Non Linearity (5)

±1.0

±2.4

LSB(max)

DNL

Differential Non Linearity

±0.5

LSB(max)

GE

Gain Error

Positive Error

−0.8

%FS(max)

Negative Error

+0.1

±3

%FS(max)

Offset Error (VIN+ = VIN−)

+0.1

±0.9

%FS(max)

Under Range Output Code

0

Over Range Output Code

4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

VCM

Common Mode Input Voltage

1.0

V

(CLK LOW)

8

pF

CIN

VIN Input Capacitance (each pin to GND)

VIN = 1.0 Vdc + 1 VP-P

(CLK HIGH)

7

pF

0.8

V(min)

VREF

Reference Voltage (6)

1.00

1.2

V(max)

Reference Input Resistance

100

M

Ω(min)

(1)

The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited

per Note 4 under the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or

below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate

conversions. See Figure 2

(2)

To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.

(4)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

(5)

Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through

positive and negative full-scale.

(6)

Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ or the

LM4051CIM3-1.2 bandgap voltage reference is recommended for this application.

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD= VDR = +3.3V, PD

= 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other

limits TA = TJ = 25°C

(1) (2) (3)

Units

Symbol

Parameter

Conditions

Typical (4)

Limits (4)

(Limits)

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

VIN(1)

Logical “1” Input Voltage

VD = 3.3V

2.0

V(min)

VIN(0)

Logical “0” Input Voltage

VD = 3.0V

0.8

V(max)

IIN(1)

Logical “1” Input Current

VIN

+, V

IN

− = 3.3V

10

µA

IIN(0)

Logical “0” Input Current

VIN

+, V

IN

− = 0V

−10

µA

CIN

Digital Input Capacitance

5

pF

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

(1)

The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited

per Note 4 under the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or

below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate

conversions. See Figure 2

(2)

To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.

(4)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

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