1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

CS

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDO

t

SU1

t

D1

t

H1

t

D2

t

D3

Sample

N

Sample

N+1

t

ACQ

t

CONV

1/f

SAMPLE

DatafromSampleN

-1

t

W1

t

WH

t

WL

t

D4

ADS7947

ADS7948

ADS7949

www.ti.com

SLAS708 – SEPTEMBER 2010

TIMING DIAGRAM

TIMING REQUIREMENTS

PARAMETER

MIN

TYP

MAX

UNIT

ADS7947 (12-bit)

13.5

SCLK

Conversion time

ADS7948 (10-bit)

10.5

SCLK

ADS7949 (8-bit)

8.5

SCLK

Acquisition time

80

ns

SCLK = 34MHz,

Sample rate (throughput rate)

2

MSPS

16 clock frame

ADS7947 (12-bit)

SCLK = 34MHz

2.1

MSPS

ADS7948 (10-bit)

SCLK = 34MHz

2.57

MSPS

ADS7949 (8-bit)

SCLK = 34MHz

3

MSPS

Pulse width CS high

25

ns

DVDD = 1.8V

14.5

ns

Delay time, CS low to first data (D0-15) out

DVDD = 3V

12.5

ns

DVDD = 5V

8.5

ns

DVDD = 1.8V

3.5

ns

Setup time, CS low to first rising edge of SCLK

DVDD = 3V

3.5

ns

DVDD = 5V

3.5

ns

DVDD = 1.8V

11

ns

(2)

Delay time, SCLK falling to SDO

DVDD = 3V

9

ns

DVDD = 5V

7.1

ns

DVDD = 1.8V

4

ns

Hold time, SCLK falling to data valid

DVDD = 3V

3

ns

DVDD = 5V

2

ns

DVDD = 1.8V

15

ns

Delay time, CS high to SDO 3-state

DVDD = 3V

12.5

ns

DVDD = 5V

8.5

ns

Delay time CS rising edge from conversion end

10

ns

Pulse duration, SCLK high

11

ns

Pulse duration, SCLK low

11

ns

SCLK frequency

0.4

34

40

MHz

Setup time, PDEN high to CS rising edge

2

ns

(refer to Figure 50 and Figure 51)

Hold time, CS rising edge to PDEN falling edge (refer to Figure 50)

20

ns

(1)

1.8V specifications apply from 1.65V to 2V; 3V specifications apply form 2.7V to 3.6V; 5V specifications apply from 4.75V to 5.25V.

(2)

With 50pF load.

Copyright © 2010, Texas Instruments Incorporated

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