Electronic Components Datasheet Search |
|
ADS7887SDCKTG4 Datasheet(PDF) 8 Page - Texas Instruments |
|
ADS7887SDCKTG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 29 page www.ti.com DEVICE INFORMATION 3 2 4 6 1 VDD GND VIN CS SCLK SDO 5 ADS7887 NORMAL OPERATION 1 2 4 5 6 14 15 CS SCLK SDO 0 0 0 D9 D8 D1 D0 13 0 0 16 td1 td2 th1 tconv 1/throughput tq td3 tw1 b tsu1 a ADS7887 ADS7888 SLAS468 – JUNE 2005 SOT23/SC70 PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. VDD 1 – Power supply input also acts like a reference voltage to ADC. GND 2 – Ground for power supply, all analog and digital signals are referred with respect to this pin. VIN 3 I Analog signal input SCLK 4 I Serial clock SDO 5 O Serial data out CS 6 I Chip select signal, active low The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format and padded by 2 lagging zeros. The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with two lagging zeros as shown in Figure 1. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 13th falling edge. This point is indicated by b in Figure 1. CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in the SPECIFICATIONS table. Figure 1. ADS7887 Interface Timing Diagram 8 |
Similar Part No. - ADS7887SDCKTG4 |
|
Similar Description - ADS7887SDCKTG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |