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ADS7887SDBVTG4 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS7887SDBVTG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 29 page www.ti.com ADS7888 NORMAL OPERATION 1 2 4 5 6 12 15 CS SCLK SDO 0 0 0 D7 D6 D1 D0 11 0 0 16 td1 td2 th1 tconv 1/throughput tq td3 tw1 b tsu1 a 0 1 2 4 5 6 12 CS SCLK SDO 0 0 0 D7 D6 D1 D0 11 td1 td2 th1 tconv 1/throughput tq th1 tw1 b tsu1 a td4 POWER DOWN MODE ADS7887 ADS7888 SLAS468 – JUNE 2005 The cycle begins with the falling edge of CS . This point is indicated as a in Figure 2. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and padded by 4 lagging zeros. The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with four lagging zeros as shown in Figure 2. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 12th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 11th falling edge. This point is indicated by b in Figure 2. CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in the SPECIFICATIONS section. Figure 2. ADS7888 Interface Timing Diagram As shown in Figure 3, the ADS7888 can achieve 1.5-MSPS throughput. CS can be pulled high after the 12th falling edge (with a 25-MHz SCLK). SDO goes to 3-state after the LSB (as CS is high). CS can be pulled low at the end of the quiet time (tq) after SDO goes to 3-state. Figure 3. ADS7888 Interface Timing Diagram, Data Transfer with 12-Clock Frame The device enters power down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power down condition as shown in Figure 4. 9 |
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