TLV1543C, TLV1543I, TLV1543M

3.3V 10BIT ANALOGTODIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

8

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recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VCC

TLV1543C/TLV1543I

3

3.3

5.5

V

Supply voltage, VCC

TLV1543M

3

3.3

3.6

V

Positive reference voltage, Vref + (see Note 2)

VCC

V

Negative reference voltage, Vref − (see Note 2)

0

V

Differential reference voltage, Vref + − Vref − (see Note 2)

2.5

VCC

VCC + 0.2

V

Analog input voltage (see Note 2)

0

VCC

V

High-level control input voltage, VIH

TLV1543C/TLV1543I

VCC = 3 V to 5.5 V

2

V

High-level control input voltage, VIH

TLV1543M

VCC = 3 V to 3.6 V

2

V

Low-level control input voltage, VIL

TLV1543C/TLV1543I

VCC = 3 V to 5.5 V

0.6

V

Low-level control input voltage, VIL

TLV1543M

VCC = 3 V to 3.6 V

0.8

V

Setup time, address bits at data input before I/O CLOCK

↑, tsu(A) (see Figure 4)

100

ns

Hold time, address bits after I/O CLOCK

↑, th(A) (see Figure 4)

0

ns

Hold time, CS low after last I/O CLOCK

↓, th(CS)

0

ns

Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3)

1.425

µs

Clock frequency at I/O CLOCK (see Note 4)

TLV1543C/TLV1543I

0

1.1

MHz

Clock frequency at I/O CLOCK (see Note 4)

TLV1543M

0

2.1

MHz

Pulse duration, I/O CLOCK high, tw(H_I/O)

190

ns

Pulse duration, I/O CLOCK low, tw(L_I/O)

190

ns

Transition time, I/O CLOCK, tt(I/O) (see Note 5)

1

µs

Transition time, ADDRESS and CS, tt(CS)

10

µs

TLV1543C

0

70

°C

Operating free-air temperature, TA

TLV1543I

−40

85

°C

Operating free-air temperature, TA

TLV1543M

−55

125

°C

NOTES:

2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

to REF− convert as all zeros (0000000000).

3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS

setup time has elapsed.

4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (

≤ 2 V), at least one I/O clock rising edge (≥ 2 V) must occur within

9.5

µs.

5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of

normal room temperature, the devices function with input clock transition time as slow as 1

µs for remote data-acquisition

applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.