TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170D –MARCH 1999 – REVISED JULY 2000

4

POST OFFICE BOX 655303

detailed description

_

+

Charge

Redistribution

DAC

SAR

Register

REFM

ADC Code

Control

Logic

Ain

Figure 1. Analog-to-Digital SAR Converter

The TLV1571/78 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a

simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process

starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

The TLV1571/ TLV1578 requires 16 CLKs for each conversion, (assuming the read cycle takes 1 CLK). The

equivalent maximum sampling frequency achievable with a given CLK frequency is:

The TLV1571 and TLV1578 are software configurable. The first two MSB bits, D(9,8) are used to address which

register to set. The rest of the eight bits are used as control data bits. There are two control registers, CR0 and

CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A

description of the control registers is shown in Figure 2.