 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TLV1504ID Datasheet(PDF) 8 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
TLV1504ID Datasheet(HTML) 8 Page - Texas Instruments |
|
|
8 / 48 page  TLV1504, TLV1508 2.7V TO 5.5V, 10BIT, 200KSPS, 4/8CHANNEL, LOW POWER SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 normal sampling When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input source resistance is high. extended sampling CSTART − An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used to have total control of the sampling period and the start of a conversion. This extended sampling is user-defined and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal to the minimum t(SAMPLE). In a select cycle used in mode 01 (REPEAT MODE), CSTART can be started as soon as the channel is selected (after the fifth SCLK). In this case the sampling period is not started until CS has become inactive. Therefore the nonoverlapped CSTART low time must meet the minimum sampling time requirement. The low-to-high transition of CSTART terminates the sampling period and starts the conversion period. The conversion clock can also be configured to use either internal OSC or external SCLK. This function is useful for an application that requires: D The use of an extended sampling period to accommodate different input source impedance D The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance at lower supply voltage. Once the conversion is complete, the processor can initiate a read cycle by using either the read FIFO command to read the conversion result or by simply selecting the next channel number for conversion. Since the device has a valid conversion result in the output buffer, the conversion result is simply presented at the serial data output. To completely get out of the extended sampling mode, CS must be toggled twice from a high-to-low transition while CSTART is high. The read cycle mentioned above followed by another configuration cycle of the ADC qualifies this condition and successfully puts the ADC back to its normal sampling mode. This can be viewed in Figure 9. Table 3. Sample and Convert Conditions CONDITIONS SAMPLE CONVERT CSTART CS = 1 (see Figures 11 and 18) No sampling clock (SCLK) required. Sampling period is totally controlled by the low time of CSTART. The high-to-low transition of CSTART (when CS=1) starts the sampling of the analog input signal. The low time of CSTART dictates the sampling period. The low-to-high transition of CSTART ends sampling period and begins the conversion cycle. (Note: this trigger only works when internal reference is selected for conversion modes 01, 10, and 11.) 1) If internal clock OSC is selected a maximum CS CSTART = 1 FS = 1 SCLK is required. Sampling period is programmable under normal sampling. When programmed to sample under short sampling, 12 SCLKs are generated to complete sampling period. 24 SCLKs are generated when programmed for long sampling. A command set to configure the device requires 4 SCLKs thereby ex- tending to 16 or 28 SCLKs respectively before conver- 1) If internal clock OSC is selected a maximum conversion time 3.86 µs can be achieved. 2) If external SCLK is selected, conversion time is tconv = 14 × DIV/f(SCLK), where DIV can be 1, 2, or 4. FS CSTART = 1 CS = 0 tending to 16 or 28 SCLKs respectively before conver- sion takes place. (Note: Because the ADC only bypasses a valid channel select command, the user can use select channel 0, 0000b, as the SDI input when either CS or FS is used as trigger for conversion. The ADC responds to commands such as SW power- down, 1000b.) |
Similar Part No. - TLV1504ID |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
