ADS7229IRSAR datasheet(9/51 Pages) TI1

Part #	ADS7229IRSAR

Description	LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

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Manufacturer	TI1 [Texas Instruments]

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TIMING CHARACTERISTICS

(1) (2): 1.8V

ADS7229

ADS7230

www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009

All specifications typical at –40°C to 85°C, +VA = 2.7 V, and +VBD = 1.8V, unless otherwise noted.

ADS7229, ADS7230

PARAMETER

MIN

TYP

MAX

UNIT

External, 3V

≤ +VA ≤ 3.6V,

0.5

21

fCCLK = 1/2 fSCLK

External, 2.7V

≤ +VA ≤ 3V,

fCCLK

Frequency, conversion clock, CCLK

0.5

18.9

MHz

fCCLK = 1/2 fSCLK

Internal,

20

22.3

23.5

fCCLK = 1/2 fSCLK

t1

Setup time, falling edge of CS to EOC

1

CCLK

t2

Hold time, falling edge of CS to EOC

0

ns

tCL

Pulse duration, CONVST low

40

ns

t3

Hold time, falling edge of CS to EOS

20

ns

t4

Setup time, rising edge of CS to EOS

20

ns

t5

Hold time, rising edge of CS to EOS

20

ns

Setup time, falling edge of CS to first t6 falling

t6

5

ns

SCLK

tSCLKL

Pulse duration, SCLK low

8

tSCLK – 8

ns

tSCLKH

Pulse duration, SCLK high

8

tSCLK – 8

ns

All modes,

23.8

2000

3V

≤ +VA ≤ 3.6V

tSCLK

Cycle time, SCLK

ns

All modes,

26.5

2000

2.7V

≤ +VA < 3V

tH2

Hold time, falling edge of SCLK to SDO invalid 10pF load

7.5

ns

tD1

Delay time, falling edge of SCLK to SDO valid

10pF load

16

ns

10pF load,

13

2.7V

≤ +VA ≤ 3V

Delay time, falling edge of CS to SDO valid,

tD2

ns

SDO MSB output

10pF load,

11

3V

≤ +VA ≤ 3.6V

tS1

Setup time, SDI to falling edge of SCLK

8

ns

tH1

Hold time, SDI to falling edge of SCLK

4

ns

Delay time, rising edge of CS/FS to SDO

tD3

8

ns

3-state

Setup time, 16th falling edge of SCLK t7

t7

10

ns

before rising edge of CS/FS

(1)

All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.

(2)

See timing diagrams.

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Product Folder Link(s): ADS7229 ADS7230

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