ADS4128_14 datasheet(52/62 Pages) TI1

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ADS4128

SBAS578 – MAY 2012

www.ti.com

Output Data Format

Two output data formats are supported: binary twos complement and offset binary. These formats can be

selected by using the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel

configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale

level.

BOARD DESIGN CONSIDERATIONS

Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of

the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout

and grounding.

Supply Decoupling

Because the ADS4128 already includes internal decoupling, minimal external decoupling can be used without

loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum

number of capacitors depends on the actual application. The decoupling capacitors should be placed very close

to the converter supply pins.

Exposed Pad

In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the

digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and

electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and

QFN/SON PCB Attachment (SLUA271), both available for download at www.ti.com.

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