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ADS4128 Datasheet(PDF) 47 Page - Texas Instruments |
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ADS4128 Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 62 page  ADS4128 www.ti.com SBAS578 – MAY 2012 OFFSET CORRECTION The ADS4128 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The correction loop time constant is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 13. Table 13. Offset Correction Loop Time Constant TIME CONSTANT, TCCLK OFFSET CORR TIME CONSTANT (Number of Clock Cycles) TIME CONSTANT, TCCLK × 1/fS (sec) (1) 0000 1 M 4 ms 0001 2 M 8 ms 0010 4 M 16.7 ms 0011 8 M 33.5 ms 0100 16 M 67 ms 0101 32 M 134 ms 0110 64 M 268 ms 0111 128 M 537 ms 1000 256 M 1.1 s 1001 512 M 2.15 s 1010 1 G 4.3 s 1011 2 G 8.6 s 1100 Reserved — 1101 Reserved — 1110 Reserved — 1111 Reserved — (1) Sampling frequency, fS = 200 MSPS. After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen, the last estimated value is used for every clock cycle offset correction. Note that offset correction is disabled by default after reset. After a reset, the device is in low-latency mode and offset correction is disabled. To use offset correction: • First, disable low-latency mode (DIS LOW LATENCY = 1). • Then set EN OFFSET CORR to '1' and program the required time constant. POWER DOWN The ADS4128 has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down, resulting in reduced total power dissipation of approximately 10 mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100 µs. To enter the global power-down mode, set the PDN GLOBAL register bit. Standby In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5 µs. The total power dissipation in standby mode is approximately 185 mW. To enter standby mode, set the STBY register bit. Output Buffer Disable The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast, approximately 100 ns. This mode can be controlled by using the PDN OBUF register bit or the OE pin. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 47 Product Folder Link(s): ADS4128 |
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