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ADC124S101 Datasheet(PDF) 7 Page - Texas Instruments

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Part # ADC124S101
Description  ADC124S101 4 Channel, 500 ksps to 1 Msps, 12-Bit A/D Converter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC124S101 Datasheet(HTML) 7 Page - Texas Instruments

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tCSU
tCLH
SCLK
CS
SCLK
tCONVERT
tACQ
Z3
Z2
Z1
Z0
DB10
DONT
DONTC ADD2
ADD1
ADD0
DONTC DONTC DONTC
DB11
DB9
DB8
DB1
16
8
7
6
5
4
3
2
1
DB0
DIN
DOUT
SCLK
CS
tEN
tCL
tACC
tDIS
tCH
tH
tSU
ADC124S101
www.ti.com
SNAS283D – MARCH 2005 – REVISED MARCH 2013
Figure 5. ADC124S101 Serial Timing Diagram
Figure 6. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold
capacitor to charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the
input signal is acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy
from one analog input that appears at the measured analog input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD
− 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below
VREF+ and is defined as:
VFSE = Vmax + 1.5 LSB – VREF+
(1)
where Vmax is the voltage at which the transition to the maximum code occurs. FSE can be
expressed in Volts, LSB or percent of full scale range.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last
code transition). The deviation of any given code from this straight line is measured from the center of that
Copyright © 2005–2013, Texas Instruments Incorporated
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