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ADS807 Datasheet(PDF) 9 Page - Texas Instruments

Part No. ADS807
Description  12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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ADS807 Datasheet(HTML) 9 Page - Texas Instruments

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ADS807
9
SBAS072A
www.ti.com
• improves the noise immunity based on the converter’s
common-mode input rejection
Using the single-ended mode, the signal is applied to one of
the inputs, while the other input is biased with a DC voltage
to the required common-mode level. Both inputs are equal in
terms of their impedance and performance, except that
applying the signal to the complementary input (IN) instead
of the IN input will invert the input signal relative to the output
code. For example, in case the input driver operates in
inverting mode, using IN as the signal input will restore the
phase of the signal to its original orientation. Time-domain
applications may benefit from a single-ended interface con-
figuration and its reduced circuit complexity. While maintain-
ing good SNR, driving the ADS807 with a single-ended
signal will result in a reduction of the distortion performance.
Employing dual-supply amplifiers and AC-coupling will usu-
ally yield the best results, while DC-coupling and/or single-
supply amplifiers impose additional design constraints due to
their headroom requirements, especially when selecting the
3Vp-p input range. However, single-supply amplifiers have
the advantage of inherently limiting their output swing to
within the supply rails. Alternatively, a voltage-limiting ampli-
fier, like the OPA688, may be considered to set fixed-signal
limits and avoid any severe over-range condition for the A/D
converter.
The full-scale input range of the ADS807 is defined by the
reference voltages. For example, setting the range select pin
to FSSEL = LOW, and using the internal references
(REFT = +3.0V and REFTB = +2.0V), the full-scale range is
defined to: FSR = 2 • (REFT – REFB) = 2Vp-p.
The trade-off of the differential input configuration versus the
single-ended is its higher complexity. In either case, the
selection of the driver amplifier should be such that the
amplifier’s performance will not degrade the A/D converter’s
performance. The ADS807 operates on a single power
supply, which requires a level shift to a ground-based bipolar
input signals to comply with its input voltage range require-
ments.
The input of the ADS807 is of a capacitive nature and the
driving source needs to provide the current to charge or
discharge the input sampling capacitor while the track-and-
hold is in track mode. This effectively results in a dynamic
input impedance which depends on the sampling frequency.
It most applications, it is recommended to add a series
resistor, typically 20
Ω to 50Ω, between the drive source and
the converter inputs. This will isolate the capacitive input
from the source, which can be crucial to avoid gain peaking
when using wideband operational amplifiers. Secondly, it will
create a 1st-order, low-pass filter in conjunction with the
specified input capacitance of the ADS807. Its cutoff fre-
quency can be adjusted even further by adding an external
shunt capacitor from each signal input to ground. The opti-
mum values of this R-C network depend on a variety of
factors which include the ADS807 sampling rate, the se-
lected op amp, the interface configuration, and the particular
application (time domain versus frequency domain). Gener-
ally, increasing the size of the series resistor and/or capacitor
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS807 is a high-speed, CMOS A/D converter which
employs a pipelined converter architecture consisting of 12
internal stages. Each stage feeds its data into the digital
error correction logic ensuring excellent differential linearity
and no missing codes at the 12-bit level. The output data
becomes valid after the rising clock edge (see Timing Dia-
gram). The pipeline architecture results in a data latency of
6 clock cycles.
The analog input of the ADS807 consists of a differential
track-and-hold circuit. The differential topology along with
tightly matched poly-poly capacitors produce a high level of
AC performance at high sampling rates and in undersampling
applications.
Both inputs (IN, IN) require external biasing using a com-
mon-mode voltage that is typically at the mid-supply level
(+VS/2).
DRIVING THE ANALOG INPUTS
The analog inputs of the ADS807 are a very high impedance.
They should be driven through an R-C network designed to
pass the highest frequency of interest. This prevents high-
frequency noise in the input from affecting SFDR and SNR.
The ADS807 can be used in a wide variety of applications
and deciding on the best performing analog interface circuit
depends on the type of application. The circuit definition
should include considerations of input frequency spectrum
and amplitude, single-ended or differential drive, and avail-
able power supplies. For example, communication (frequency
domain) applications process frequency bands not including
DC. In imaging (time domain) applications, the input DC
component must be maintained into the A/D converter.
Features of the ADS807, including full-scale select (FSSEL),
external reference, and CM output provide flexibility to ac-
commodate a wide range of applications. The ADS807
should be configured to meet application objectives while
observing the headroom requirements of the driving amplifi-
ers to yield the best overall performance.
The ADS807 input structure allows it to be driven either
single-ended or differentially. Differential operation of the
ADS807 requires an in-phase input signal and a 180
° out-of-
phase part simultaneously applied to the inputs (IN, IN). The
differential operation offers a number of advantages which,
in most applications, will be instrumental in achieving the
best dynamic performance of the ADS807:
• the signal swing is half of that required for the single-
ended operation and therefore, is less demanding to
achieve while maintaining good linearity performance from
the signal source
• the reduced signal swing allows for more headroom in the
interface circuitry and therefore, a wider selection of the
best suitable driver op amp
• even-order harmonics are minimized


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