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80960KB Datasheet(PDF) 7 Page - Intel Corporation |
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80960KB Datasheet(HTML) 7 Page - Intel Corporation |
7 / 44 page 1 80960KB 1.0 THE i960® PROCESSOR The 80960KB is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in interrupt controller. The 80960KB has a large register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess of 9.4 million instructions per second*. The 80960KB is well-suited for a wide range of applications including non-impact printers, I/O control and specialty instrumentation. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and networking. These types of * Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment Corporation) applications require high integration, low power consumption, quick interrupt response times and high performance. Since time to market is critical, embedded microprocessors need to be easy to use in both hardware and software designs. All members of the i960 processor family share a common core architecture which utilizes RISC technology so that, except for special functions, the family members are object-code compatible. Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market. Software written for the 80960KB will run without modification on any other member of the 80960 Family. It is also pin-compatible with the 80960KA and the 80960MC which is a military-grade version that supports multitasking, memory management, multiprocessing and fault tolerance. Figure 2. 80960KB Programming Environment INSTRUCTION CACHE INSTRUCTION STREAM FETCH LOAD STORE SIXTEEN 32-BIT GLOBAL REGISTERS g0 g15 SIXTEEN 32-BIT LOCAL REGISTERS REGISTER CACHE FOUR 80-BIT FLOATING POINT REGISTERS r0 r15 CONTROL REGISTERS INSTRUCTION EXECUTION INSTRUCTION POINTER ARITHMETIC CONTROLS PROCESS CONTROLS TRACE CONTROLS ARCHITECTURALLY DEFINED DATA STRUCTURES FFFF FFFFH 0000 0000H ADDRESS SPACE PROCESSOR STATE REGISTERS |
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