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TPS3700 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS3700 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 23 page  TPS3700 www.ti.com SBVS187C – FEBRUARY 2012 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS Over the operating temperature range of TJ = –40°C to +125°C, and 1.8 V < VDD < 18 V, unless otherwise noted. Typical values are at TJ = +25°C and VDD = 5 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD Supply voltage range 1.8 18 V V(POR) Power-on reset voltage(1) VOL (max) = 0.2 V, I(OUT) = 15 µA 0.8 V VDD = 1.8 V 396 400 404 mV VITP Positive-going input threshold voltage VDD = 18 V 396 400 404 mV VDD = 1.8 V 387 394.5 400 mV VITN Negative-going input threshold voltage VDD = 18 V 387 394.5 400 mV VHYS Hysteresis voltage (HYS = VITP – VITN) 5.5 12 mV VDD = 1.8 V and 18 V, VIN = 6.5 V –25 1 25 nA IIN Input current (at IN pin) VDD = 1.8 V and 18 V, VIN = 0.1 V –15 1 15 nA VDD = 1.3 V, IOUT = 0.4 mA 250 mV VOL Low-level output voltage VDD = 1.8 V, IOUT = 3 mA 250 mV VDD = 5 V, IOUT = 5 mA 250 mV VDD = 1.8 V and 18 V, VOUT = VDD 300 nA Ilkg(OD) Open-drain output leakage current VDD = 1.8 V, VOUT = 18 V 300 nA VDD = 5 V, 10-mV input overdrive, tpd(HL) High-to-low propagation delay(2) 18 µs RL = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV VDD = 5 V, 10-mV input overdrive, tpd(LH) Low-to-high propagation delay(2) 29 µs RL = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV VDD = 5 V, 10-mV input overdrive, tR Output rise time 2.2 µs RL = 10 kΩ, VO = (0.1 to 0.9) × VDD VDD = 5 V, 10-mV input overdrive, tF Output fall time 0.22 µs RL = 10 kΩ, VO = (0.1 to 0.9) × VDD VDD = 1.8 V, no load 5.5 11 µA VDD = 5 V 6 13 µA IDD Supply current VDD = 12 V 6 13 µA VDD = 18 V 7 13 µA Startup delay(3) 150 µs UVLO Undervoltage lockout(4) VDD falling 1.3 1.7 V (1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined. (2) High-to-low and low-to-high refers to the transition at the input pins (INA+ and INB–). (3) During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state. (4) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR). Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS3700 |
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