A8285SLB-T datasheet(5/18 Pages) ALLEGRO

Part #	A8285SLB-T

Description	LNB Supply and Control Voltage Regulator

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Manufacturer	ALLEGRO [Allegro MicroSystems]

Direct Link	http://www.allegromicro.com

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5 / 18 page

LNB Supply and Control Voltage Regulator

A8285 and

A8287

5

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS

(continued) at TA = +25°C, VIN = 10 to 16 V (unless otherwise noted)

Characteristics

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Tone Characteristics

Tone Frequency

fTONE

–

20

22

24

kHz

Tone Pull-Down Current

ITONE

–30

40

50

mA

Tone Turn-On and Turn-Off Delays

tDEL

Using EXTM pin

–

1

μs

External Tone Logic Input

VIH

–2

–

V

VIL

–

0.8

V

Input Leakage

IIL

––1

–

1

μA

Tone Detector Input Amplitude

VTDI

fIN = 22 kHz

260

–

1000

mV

Tone Detector Frequency Capture

fTDI

600 mVpp sinewave

17.6

–

26.4

kHz

Tone Detector Input Impedance

ZTDI

See note 1

–

8.6

–

k



Tone Detector Output Voltage

VOL

Tone present, ILOAD = 3 mA

–

0.4

V

Tone Detector Output Leakage

IOL

Tone absent, VO = 7 V

–

10

A

I2C Interface

Logic Input (SDA,SCL) Low Level

VIL

–

0.8

V

Logic Input (SDA,SCL) High Level

VIH

–2

–

V

Input Hysteresis

VHYS

–

150

–

mV

Logic Input Current

IIN

VIN = 0 V to 7 V

–10

<±1.0

10

μA

Output Voltage (SDA, IRQ)

VOL

ILOAD = 3 mA

–

0.4

V

Output Leakage (SDA, IRQ)

IOL

VO = 0 V to 7 V

–

10

μA

SCL Clock Frequency

fCLK

–

0

–

400

kHz

Output Fall Time

tOF

VIH to VIL

–

250

ns

Bus Free Time Between Stop and Start

tBUF

See I2C Interface Timing Diagram

1.3

–

μs

Hold Time for Start Condition

tHD:STA

See I2C Interface Timing Diagram

0.6

–

μs

Setup Time for Start Condition

tSU:STA

See I2C Interface Timing Diagram

0.6

–

μs

SCL Low Time

tLOW

See I2C Interface Timing Diagram

1.3

–

μs

SCL High Time

tHIGH

See I2C Interface Timing Diagram

0.6

–

μs

Data Setup Time

tSU:DAT

See note1; I2C Interface Timing Diagram

100

–

ns

Data Hold Time

tHD:DAT

See I2C Interface Timing Diagram

0

–

900

ns

Setup Time for Stop Condition

tSU:STO

See I2C Interface Timing Diagram

0.6

–

μs

Continued on next page

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