NCP1090, NCP1091, NCP1092

http://onsemi.com

8

Example for a Targeted Uvlo_on of 35 V:

Let’s start with a Rdet of 30.1 k

Ω. This gives a Ruvlo of

144 k

Ω made with a Ruvlo2 of 4.99 kΩ and a Ruvlo1 of

140 k

Ω (closest values from E96 series). Note that there is

a pull down current of 2.5

mA typ on the UVLO. Assuming

the previous example, this pull down current will create a

(non critical) systematic offset of 350 mV on the Uvlon_on

level of 35 V.

The external UVLO hysteresis on the NCP1091 is about

15 percent typical.

Inrush and Operational Current Limitations

Both inrush and operational current limit are defined by

an external Rinrush resistor connected between INRUSH

and VPORTN. The low inrush current limit allows smooth

charge of large dc−dc converter input capacitor by limiting

the power dissipation over the internal pass switch. In power

mode, the operational current limit protects the pass switch

and the PD application against excessive transient current

and failure on the dc−dc converter output.

Once the input supply reached the Vulvo_on level, the

charge of Cpd capacitor starts with a current limitation set to

to the INRUSH level. When this capacitor is fully charged,

the current limit switches without any spikes from the inrush

current to the operational current level and the power good

indicator on PGOOD pin is turned on. The capacitor is

considered to be fully charged once the following conditions

are satisfied:

1. The drain−source voltage of the Pass Switch has

decreased below the Vds_pgood_on level (typical

1V)

2. The gate−source voltage of the Pass Switch is

sufficiently high (above 2 V typical) which means

the current in the pass switch has decreased below

the current limit.

This mechanism is depicted in the following Figure 7.

Operational current limit

VPORTNx

Pass Switch

Inrush current limit

RTN

0

1

VDDA1

VDDA1

1 V / 10 V

2 V

Delay

&

detector

PGOOD

Pgood_on

RTN

Pgood_on

Sense Resistor

Vds_pgood comparator

Vgs_pgood comparator

Figure 7. Inrush and Operational Current Limitation Selection Mechanism

100 mS

The operational current limit and the power good

indicator stays active as long as RTN voltage stays below the

vds_pgood_off threshold (10 V typical) and the input supply

stay above the Vulvo_off level. Therefore, fast and large

voltage step lower than 10 V are tolerated on the input

without interruption of the converter controller. Higher

input transient will not affect the behavior if RTN does not

exceed 10 V for more than 100

mS. Such input voltage steps

may be introduced by a PSE which is switched to a higher

power supply. In case RTN is still above 10 V after this delay,

the power good is turned off and the pass switch current limit

falls back to the inrush level.

PGOOD Indicator

The NCP1090/91/92 integrate a Power Good indicator

circuitry indicating the end of the dc−dc converter input

capacitor charge, and the enabling of the operational current

limit. This indicator is implemented on the PGOOD pin

which goes in open drain state when active and which is

pulled to ground during turn off.

A possible usage of this PGOOD pin is illustrated in

Figure 8. During the inrush phase, the converter controller

is forced in standby mode due to the PGOOD pin forcing low

the under voltage lock out pin of the controller. Once the Cpd

capacitor is fully charged, PGOOD goes in open drain state,

allowing the start up sequence of the converter controller.