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TMS370C311A Datasheet(PDF) 6 Page - Texas Instruments

Part # TMS370C311A
Description  8-BIT MICROCONTROLLER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS370C311A Datasheet(HTML) 6 Page - Texas Instruments

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TMS370Cx1x
8-BIT MICROCONTROLLER
SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
central processing unit (CPU) (continued)
Figure 1 illustrates the CPU registers and memory blocks.
Reserved
Peripheral File
Not Available
100Fh
1010h
1F00h
1FFFh
2000h
5FFFh
6000h
77FFh
7800h
Interrupts and Reset Vectors;
Trap Vectors
104Fh
1050h
1EFFh
Reserved
7FFFh
0
RAM (Includes up to 256-Byte Registers File)
0
15
Program Counter
7
Legend:
Z=Zero
IE1=Level 1 interrupts Enable
C=Carry
V=Overflow
N=Negative
IE2=Level 2 interrupts Enable
IE1
IE2
Z
N
C
0
1
2
3
4
5
6
7
V
Status Register (ST)
Stack Pointer (SP)
R0(A)
R1(B)
R3
R127
0000h
0001h
0002h
007Fh
R255
0003h
R2
00FFh
256-Byte Data EEPROM
2K-Byte ROM (7800h--7FFFh)
6FFFh
7000h
8K-Byte ROM/EPROM (6000h--7FFFh)
4K-Byte ROM (7000h--7FFFh)
7FC0h
7FBFh
128-Byte RAM (0000h--007Fh)
007Fh
0080h
00FFh
0100h
256-Byte RAM (0000h--00FFh)
0000h
Reserved means the address space is reserved for future expansion.
Not available means the address space is not accessible.
Figure 1. Programmer’s Model
A memory map includes:
D
128- or 256-byte general-purpose RAM that can be used for data memory storage, program instructions,
general purpose register, or the stack
D
A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and
EEPROM/EPROM programming control
D
256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off
conditions
D
2K-, 4K-, or 8K-byte ROM or 8K-byte EPROM
stack pointer (SP)
The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. Typically, the stack
is used to store the return address on subroutine calls as well as the status register (ST) contents during interrupt
sequences.
The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed
onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the
on-chip RAM.


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