Electronic Components Datasheet Search |
|
TSB12LV26PZTG4 Datasheet(PDF) 1 Page - Texas Instruments |
|
TSB12LV26PZTG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 6 page www.ti.com FEATURES DESCRIPTION TSB12LV26 TSB12LV26I SLLA214 – JUNE 2006 OHCI-Lynx™ PCI-Based IEEE 1394 Host Controller • External cycle timer control for customized synchronization • 3.3-V and 5-V PCI bus signaling • PCI burst transfers and deep FIFOs to • 3.3-V supply (core voltage is internally tolerate large host latency regulated to 1.8 V) • Two general-purpose I/Os • Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s • Fabricated in advanced low-power CMOS process • Physical write posting of up to three outstanding transactions • Packaged in 100-terminal LQFP (PZT) • Serial ROM interface supports 2-wire devices • PCI_CLKRUN protocol The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates. As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99 Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states. The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data. The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface. An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to 33 MHz. NOTE: This product is for high-volume PC applications only. For a complete datasheet or more information contact support@ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OHCI-Lynx is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Similar Part No. - TSB12LV26PZTG4 |
|
Similar Description - TSB12LV26PZTG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |