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MB86330 Datasheet(PDF) 15 Page - Fujitsu Component Limited. |
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MB86330 Datasheet(HTML) 15 Page - Fujitsu Component Limited. |
15 / 46 page 15 MB86330 s BASIC PIPELINE OPERATION The DSP splits the contents of processing in one cycle to increase the number of pipeline sectors for high-speed operation. For operations using product adders such as product addition and multiplication, and for operations using 40-bit adders such as 40-bit addition, the processing latency is two cycles. s PRODUCT ADDITION For product addition and multiplication, the latency is two cycles. Because it is provided with a dual product adder (MAC) for alternate processing every cycle, however, the DSP can process n successive product addition (multiplication) steps in (n + 1) cycles. PC Pipeline phase Operation (latency 1) Operation (latency 2) Transfer (Reg-Reg R/W) Transfer (Mem Read) Transfer (Mem Write) DE1 DE2 EX1 EX2 PC PC PC PC dec1 adr dec2 ALU1 dec1 R/W dec1 ALU2 dec1 R PC dec1 [adr] W adr dec2 adr dec2 adr dec2 adr dec2 PC: Program fetch cycle DE1: Decode 1st. cycle DE2: Decode 2nd. cycle EX1: Execute 1st. cycle EX2: Execute 2nd. cycle dec1: 1st. decoding dec2: 2nd. decoding adr: Address generation [adr] Address maintenance ALU: Operation R: Reading W: Writing MSM (1) Operation latency 2 (n + 1) cycles MSM (2) MSM (3) MSM (4) MSM (n - 1) MSM (n) |
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