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AFE7222 Datasheet(PDF) 74 Page - Texas Instruments |
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AFE7222 Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 107 page  B0108-03 21-Bit Integration Counter Clear 58-Bit Integrator 58-Bit Register 9-Bit Sync Delay Counter 21-Bit Interval Counter Transfer Sync Delay (in 8 Sample Increments) Integration (in 8 Sample Increments) 21 21 9 RMS Power I Q 33 32 16 Interval (in 8 Sample Increments) INTRV_CNT(20:0) INTGR_CNT(20:0) SYNC_CNT(8:0) 16 32 Interrupt NCO SYNC SYNC SYNC SYNC SYNC TX A input (I channel) TX B input (Q channel) TX A output TX B output DAC_DCLKIN DAC_CLK %1,2,4 DAC_CLK AFE7222 AFE7225 SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com Figure 9-5. Power Meter Detailed Diagram The power meter timing is shown below: Figure 9-6. Power Meter Timing 9.8 TRANSMIT SIGNAL CHAIN Figure 9-7. Transmit Signal Chain 9.9 TRANSMIT DAC The transmit DAC is a current-steering architecture, capable of clock rates up to 250MSPS and output currents up to 20mA. The DAC is structured as a current sink from the load. The DAC is powered from AVDD3_DAC, a 3V analog supply. This provides for an output compliance range of AVDD3_DAC ± 0.5V. To benefit from the full 1V swing available on each DAC output pin, a voltage divider load referenced to a higher voltage supply, like 5V, is recommended. The current-steering architecture will sink current into the + and – DAC outputs. The sum of the current will always be equal to the full-scale current. The full scale current is set with a resistor (RBIAS) to ground on the BIASJ pin, and will be equal to 74 APPLICATION INFORMATION Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE7222 AFE7225 |
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