Electronic Components Datasheet Search |
|
LM20323 Datasheet(PDF) 20 Page - Texas Instruments |
|
|
LM20323 Datasheet(HTML) 20 Page - Texas Instruments |
20 / 28 page LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Figure 10. Safe Thermal Operating Areas (IOUT = 2.5A) The dashed lines in the figures above show an approximation of the minimum and maximum duty cycle limitations; while, the solid lines define areas of operation for a given ambient temperature. This data for the figure was derived assuming the device is operating at 3A continuous output current on a 4 layer PCB with an copper area greater than 4 square inches exhibiting a thermal characteristic less than 27 °C/W. Since the internal losses are dominated by the FETs a slight reduction in current by 500mA allows for much larger regions of operation, as shown in Figure 9. Figure 11, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. To provide an optimal thermal connection, a 5 x 4 array of 12 mil thermal vias located under the thermal pad was used to connect the 4 layers. Figure 11. Thermal Resistance vs PCB Area (4 Layer Board) PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched at high slew rates. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 12). To minimize both loop areas the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output capacitor should consist of a small localized top side plane that connects to GND and the exposed pad (EP). The inductor should be placed as close as possible to the SW pin and output capacitor. 20 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 |
Similar Part No. - LM20323 |
|
Similar Description - LM20323 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |