cv

S

R

R

Q

GND

FB

SW

VIN

EN

+

-

DRIVER

Artificial

Ramp

SHDN

Thermal

SHDN

OVP

1.6 MHz

Comp

Internal -

SENSE

I

LIMIT

I

LDO

Internal -

START

SOFT -

PFET

SENSE

I

ENABLE and UVLO

15

.

1

x

REF

V

Control Logic

LMR10510

SNVS727A – OCTOBER 2011 – REVISED OCTOBER 2011

www.ti.com

Simplified Block Diagram

Figure 20.

APPLICATIONS INFORMATION

THEORY OF OPERATION

The following operating description of the LMR10510 will refer to the Simplified Block Diagram (Figure 20) and to

the waveforms in Figure 21. The LMR10510 supplies a regulated output voltage by switching the internal PMOS

control switch at constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the

reset pulse generated by the internal oscillator. When this pulse goes low, the output control logic turns on the

generates an output proportional to the switch current. The sense signal is summed with the regulator’s

corrective ramp and compared to the error amplifier’s output, which is proportional to the difference between the

next switching cycle begins. During the switch off-time, inductor current discharges through the Schottky catch

The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage.

8

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