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DS91C176 Datasheet(PDF) 3 Page - Texas Instruments |
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DS91C176 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 20 page ![]() xxx xxx xxx High High Low Low 0 V 2.4 V -2.4 V 50 mV -50 mV 150 mV Transition Region Type 1 Type 2 VID DS91C176, DS91D176 www.ti.com SNLS146K – MARCH 2006 – REVISED NOVEMBER 2009 Connection and Logic Diagram Figure 1. Top View M-LVDS Receiver Types The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short circuits at the input will always result in the output stage being driven to a low logic state. Figure 2. M-LVDS Receiver Input Thresholds These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS91C176 DS91D176 |
Similar Part No. - DS91C176_14 |
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Similar Description - DS91C176_14 |
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