DS90LV001

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SNLS067E – JANUARY 2001 – REVISED APRIL 2013

DS90LV001 800 Mbps LVDS Buffer

Check for Samples: DS90LV001

1

FEATURES

DESCRIPTION

The DS90LV001 LVDS-LVDS Buffer takes an LVDS

2

•

Single +3.3 V Supply

input signal and provides an LVDS output signal. In

•

LVDS Receiver Inputs Accept LVPECL Signals

many large systems, signals are distributed across

•

TRI-STATE Outputs

backplanes, and one of the limiting factors for system

speed is the "stub length" or the distance between

•

Receiver Input Threshold < ±100 mV

the transmission line and the unterminated receivers

•

Fast Propagation Delay of 1.4 ns (Typ)

on

individual

cards.

Although

it

is

generally

•

Low Jitter 800 Mbps Fully Differential Data

recognized that this distance should be as short as

Path

possible to maximize system performance, real-world

packaging concerns often make it difficult to make the

•

−1

stubs as short as the designer would like.

Data Pattern at 800 Mbps

The DS90LV001, available in the WSON package,

•

Compatible with ANSI/TIA/EIA-644-A LVDS

will allow the receiver to be placed very close to the

Standard

main

transmission

line,

thus

improving

system

•

8 pin SOIC and Space Saving (70%) WSON

performance.

Package

A

wide

input

dynamic

range

will

allow

the

•

Industrial Temperature Range

DS90LV001

to

receive

differential

signals

from

LVPECL as well as LVDS sources. This will allow the

device to also fill the role of an LVPECL-LVDS

translator.

An output enable pin is provided, which allows the

user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options,

an 8 pin WSON and SOIC.

Connection Diagram

Figure 1. Top View

See Package Number D (R-PDSO-G8), NGK0008A

Block Diagram

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PRODUCTION DATA information is current as of publication date.

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Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

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