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TLV320AIC3262 Datasheet(PDF) 28 Page - Texas Instruments |
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TLV320AIC3262 Datasheet(HTML) 28 Page - Texas Instruments |
28 / 65 page t h(WS) WCLK BCLK DOUT DIN t L(BCLK) t H(BCLK) t s(WS) t d(DO-WS) t d(DO-BCLK) t h(DI) t s(DI) TLV320AIC3262 SLAS679 – DECEMBER 2011 www.ti.com Figure 4. I2S/LJF/RJF Timing in Slave Mode Table 3. I2S/LJF/RJF Timing in Slave Mode (see Figure 4) PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS MIN MAX MIN MAX tH (BCLK) BCLK high period 30 30 ns tL (BCLK) BCLK low period 30 30 ts (WS) WCLK setup 4 4 th (WS) WCLK hold 4 4 td (DO-WS) WCLK to DOUT delay (For LJF mode only) 22 20 td (DO-BCLK) BCLK to DOUT delay 22 20 ts(DI) DIN setup 4 4 th(DI) DIN hold 4 4 tr BCLK Rise time 5 4 tf BCLK Fall time 5 4 28 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3262 |
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