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LMX2485 Datasheet(PDF) 22 Page - Texas Instruments |
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LMX2485 Datasheet(HTML) 22 Page - Texas Instruments |
22 / 43 page LMX2485, LMX2485E SNAS236E – OCTOBER 2005 – REVISED FEBRUARY 2008 www.ti.com POWER PINS, POWER DOWN, AND POWER UP MODES It is recommended that all of the power pins be filtered with a series 18 ohm resistor and then placing two capacitors shunt to ground, thus creating a low pass filter. Although it makes sense to use large capacitor values in theory, the ESR (Equivalent Series Resistance) is greater for larger capacitors. For optimal filtering minimize the sum of the ESR and theoretical impedance of the capacitor. It is therefore recommended to provide two capacitors of very different sizes for the best filtering. 1 µF and 100 pF are typical values. The small capacitor should be placed as close as possible to the pin. The power down state of the LMX2485 is controlled by many factors. The one factor that overrides all other factors is the CE pin. If this pin is low, the part will be powered down. Asserting a high logic level on this pin is necessary to power up the chip, however, there are other bits in the programming registers that can override this and put the PLL back in a power down state. Provided that the voltage on the CE pin is high, programming the RF_PD and IF_PD bits to zero guarantees that the part will be powered up. Programming either one of these bits to one will power down the appropriate section of the synthesizer, provided that the ATPU bit does not override this. CE Pin RF_PD ATPU PLL State Bit Enabled + Write to RF N Counter Low X X Powered Down (Asynchronous) High X Yes Powered Up High 0 No Powered Up High 1 No Powered Down (Asynchronous) DIGITAL LOCK DETECT OPERATION The RF PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector to a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less than the ε RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater δ. The values of ε and δ are dependent on which PLL is used and are shown in the table below: PLL ε δ RF 10 ns 20 ns IF 15 ns 30 ns When the PLL is in the power down mode and the Ftest/LD pin is programmed for the lock detect function, it is forced LOW. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to divide the comparison frequency presented to the lock detect circuit by 4. Note that if the MUX[3:0] word is set such as to view lock detect for both PLLs, an unlocked (LOW) condition is shown whenever either one of the PLLs is determined to be out of lock. 22 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Links: LMX2485 LMX2485E |
Similar Part No. - LMX2485_14 |
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Similar Description - LMX2485_14 |
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