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DP83849IF Datasheet(PDF) 7 Page - Texas Instruments |
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DP83849IF Datasheet(HTML) 7 Page - Texas Instruments |
7 / 104 page DP83849IF www.ti.com SNOSAX8C – JUNE 2008 – REVISED APRIL 2009 2.4 Pin Descriptions The DP83849IF pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • JTAG Interface • Reset and Power Down • Strap Options • 10/100 Mb/s PMD Interface • Special Connect Pins • Power and Ground Pins NOTE Strapping pin option. Please see Section 2.4.2 for strap definitions. All DP83849IF signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. Type: I Input Type: O Output Type: I/O Input/Output Type OD Open Drain Type: PD,PU Internal Pulldown/Pullup Type: S Strapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap value is to be changed then an external 2.2 k Ω resistor should be used. Please see Section 2.4.2 for details.) Table 2-1. SERIAL MANAGEMENT INTERFACE Signal Name Type Pin # Description MDC I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 k Ω pullup resistor. Copyright © 2008–2009, Texas Instruments Incorporated Device Information 7 Submit Documentation Feedback Product Folder Links: DP83849IF |
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