Si4420

12

Control Commands

Control Command

Related Parameters/Functions

Related control bits

1

Configuration Setting Command

Frequency band, crystal oscillator load capacitance,

TX register, RX FIFO

el, ef, b1 to b0, x3 to x0

2

Power Management Command

Receiver/Transmitter mode change, synthesizer, xtal

osc, PA, wake-up timer, clock output can be enabled

here

er, ebb, et, es, ex, eb, ew, dc

3

Frequency Setting Command

Frequency of the local oscillator/carrier signal

f11 to f0

4

Data Rate Command

Bit rate

cs, r6 to r0

5

Receiver Control Command

Function of pin 16, Valid Data Indicator, baseband

bw, LNA gain, digital RSSI threshold

p16, d1 to d0, i2 to i0, g1 to g0, r2

to r0

6

Data Filter Command

Data filter type, clock recovery parameters

al, ml, s, f2 to f0

7

FIFO and Reset Mode Command

Data FIFO IT level, FIFO start control, FIFO enable

and FIFO fill enable

f3 to f0, al, ff, dr

8

Receiver FIFO Read Command

RX FIFO can be read with this command

9

AFC Command

AFC parameters

a1 to a0, rl1 to rl0, st, fi, oe, en

10

TX Configuration Control Command

Modulation parameters, output power, ea

mp, m3 to m0, p2 to p0

11

Transmitter Register Write Command

TX data register can be written with this command

t7 to t0

12

Wake-Up Timer Command

Wake-up time period

r4 to r0, m7 to m0

13

Low Duty-Cycle Command

Enable low duty-cycle mode. Set duty-cycle.

d6 to d0, en

14

Low Battery Detector and

Microcontroller Clock Divider

Command

LBD voltage and microcontroller clock division ratio

d2 to d0, v4 to v0

15

Status Read Command

Status bits can be read out

In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of

the command registers after power-on.

Description of the Control Commands

1. Configuration Setting Command

Bit

15

14

13

12

11

10

98765432

10

POR

100000

00

el

ef

b1

b0

x3

x2

x1

x0

8008h

Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level.

Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.

b1

b0

Frequency Band {MHz]

0

0

315

0

1

433

1

0

868

1

1

915

x3

x2

x1

x0

Crystal Load Capacitance [pF]

0000

8.5

0001

9.0

0010

9.5

0011

10.0

1110

15.5

1111

16.0

…