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AFE5809 Datasheet(PDF) 91 Page - Texas Instruments |
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AFE5809 Datasheet(HTML) 91 Page - Texas Instruments |
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91 / 100 page  AFE5809 www.ti.com SLOS738D – SEPTEMBER 2012 – REVISED JANUARY 2014 The partial power down function allows the AFE5809 to be wake up from a low-power state quickly. This configuration ensures that the external capacitors are discharged slowly; thus a minimum wake-up time is needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2 μs or 1% of the power down duration whichever is larger. The longest wake-up time depends on the capacitors connected at INP and INM, as the wake-up time is the time required to recharge the caps to the desired operating voltages. For 0.1 μF at INP and 15 nF at INM can give a wake-up time of 2.5 ms. For larger capacitors this time will be longer. The ADC wake-up time is about 1 μs. Thus the AFE5809 wake-up time is more dependent on the VCA wake-up time. This also assumes that the ADC clock has been running for at least 50 µs before normal operating mode resumes. The power-down time is instantaneous, less than 1 µs. This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical. The pulse repetition frequency of a ultrasound system could vary from 50KHz to 500 Hz, while the imaging depth (that is the active period for a receive path) varies from 10 μs to hundreds of µs. The power saving can be pretty significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC keeps running normally to ensure minimal impact to FPGAs. In the partial power-down mode, the AFE5809 typically dissipates only 26 mW/ch, representing an 80% power reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA and PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN). Complete Power-Down Mode To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5809 can be placed into a complete power-down mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN or PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the AFE5809 are powered down; and the capacitors connected to the AFE5809 are discharged. The wake-up time depends on the time needed to recharge these capacitors. The wake-up time depends on the time that the AFE5809 spends in shutdown mode. 0.1 μF at INP and 15 nF at INM can give a wake-up time close to 2.5 ms. Power Saving in CW Mode Usually only half the number of channels in a system are active in the CW mode. Thus the individual channel control through ADC_PDN_CH <7:0> and VCA_PDN_CH <7:0> can power down unused channels and save power consumption greatly. Under the default register setting in the CW mode, the voltage controlled attenuator, PGA, and ADC are still active. During the debug phase, both the PW and CW paths can be running simultaneously. In real operation, these blocks need to be powered down manually. TEST MODES The AFE5809 includes multiple test modes to accelerate system development. The ADC test modes have been discussed in the register description section. The VCA has a test mode in which the CH7 and CH8 PGA outputs can be brought to the CW pins. By monitoring these PGA outputs, the functionality of VCA operation can be verified. The PGA outputs are connected to the virtual ground pins of the summing amplifier (CW_IP_AMPINM/P, CW_QP_AMPINM/P) through 5-k Ω resistors. The PGA outputs can be monitored at the summing amplifier outputs when the LPF capacitors CEXT are removed. Please note that the signals at the summing amplifier outputs are attenuated due to the 5-k Ω resistors. The attenuation coefficient is RINT/EXT / 5 kΩ. If users would like to check the PGA outputs without removing CEXT, an alternative way is to measure the PGA outputs directly at the CW_IP_AMPINM/P and CW_QP_AMPINM/P when the CW summing amplifier is powered down Some registers are related to this test mode. PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0]. Based on the buffer amplifier configuration, the registers can be set in different ways: • Configuration 1 – In this configuration, the test outputs can be monitored at CW_AMPINP/M – Reg59[9] = 1; Test mode enabled – Reg59[8] = 0; Buffer amplifier powered down • Configuration 2 Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 91 Product Folder Links: AFE5809 |
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