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TAS5614LA Datasheet(PDF) 9 Page - Texas Instruments

Part No. TAS5614LA
Description  150-W Stereo / 300-W Mono PurePath™ HD Digital-Input Class-D Power Stage
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TAS5614LA Datasheet(HTML) 9 Page - Texas Instruments

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TAS5614LA
www.ti.com
SLAS846 – MAY 2012
AUDIO SPECIFICATION MONO (PBTL)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and
a TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12V, RL = 4Ω, fS = 384kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM =
10
μH, CDEM = 1μF, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 2 Ω, 10%, THD+N
300
RL = 3 Ω, 10% THD+N
200
RL = 4 Ω, 10% THD+N
160
PO
Power output per channel
W
RL = 2 Ω, 1% THD+N
250
RL = 3 Ω, 1% THD+N
160
RL = 4 Ω, 1% THD+N
130
THD+N
Total harmonic distortion + noise
1 W, 1 kHz signal
0.025
%
Vn
Output integrated noise
A-weighted, AES17 measuring filter
180
μV
VOS
Output offset voltage
No signal
10
20
mV
SNR
Signal to noise ratio(1)
A-weighted, AES17 measuring filter
105
dB
DNR
Dynamic range
A-weighted, –60 dBFS (rel 1% THD)
105
dB
Power dissipation due to idle losses
Pidle
PO = 0, All channels switching
(2)
1.6
W
(IPVDD_X)
(1)
SNR is calculated relative to 1% THD-N output level.
(2)
Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as a
DVDD
VDD = 12 V
3.0
3.3
3.6
V
reference node
Voltage regulator, only used as a
AVDD
VDD = 12 V
7.8
V
reference node
Operating, 50% duty cycle
20
IVDD
VDD supply current
mA
Idle, reset mode
20
50% duty cycle
9
IGVDD_X
Gate-supply current per full-bridge
mA
Reset mode
2
50% duty cycle without load
23
IPVDD_X
Full-bridge idle current
RESET low
1.9
mA
VDD and GVDD_X at 0V
0.35
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side
RDS(on), LS
60
100
m
(LS)
TJ = 25°C, excludes metalization resistance,
GVDD = 12 V
Drain-to-source resistance, high side
RDS(on), HS
60
100
m
(HS)
I/O PROTECTION
Vuvp,GVDD
8.5
V
Undervoltage protection limit, GVDD_X
Vuvp,GVDD, hyst
(1)
0.7
V
Vuvp,VDD
8.5
V
Undervoltage protection limit, VDD
Vuvp,VDD, hyst
(1)
0.7
V
Vuvp,PVDD
8.5
V
Undervoltage protection limit, PVDD_X
Vuvp,PVDD,hyst
(1)
0.7
V
OTW(1)
Overtemperature warning
115
125
135
°C
Temperature drop needed below OTW
OTWhyst
(1)
temperature for OTW to be inactive
25
°C
after OTW event.
OTE(1)
Overtemperature error
145
155
165
°C
(1)
Specified by design.
Copyright © 2012, Texas Instruments Incorporated
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