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SRC4382 Datasheet(PDF) 7 Page - Texas Instruments |
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SRC4382 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 84 page  www.ti.com ELECTRICAL CHARACTERISTICS: I 2C Standard and Fast Modes SRC4382 SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007 All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. SRC4382 PARAMETER CONDITIONS MIN TYP MAX UNITS HOST INTERFACE: I2C Standard Mode(1) SCL Clock Frequency, fSCL 0 100 kHz Hold Time Repeated START Condition, tHDSTA 4 μs Low Period of SCL Clock, tLOW 4.7 μs High Period of SCL Clock, tHIGH 4 μs Setup Time Repeated START Condition, tSUSTA 4.7 μs Data Hold Time, tHDDAT 0(2) 3.45(3) μs Data Setup Time, tSUDAT 250 ns Rise Time for Both SDA and SDL, tR 1000 ns Fall Time for Both SDA and SDL, tF 300 ns Setup Time for STOP Condition, tSUSTO 4 μs Bus Free Time Between START and STOP, tBUF 4.7 μs Capacitive Load for Each Bus Line, CB 400 pF Noise Margin at Low Level (including hysteresis), VNL 0.1 נ VIO V Noise Margin at High Level (including hysteresis), VNH 0.2 נ VIO V HOST INTERFACE: I2C Fast Mode(1) SCL Clock Frequency, fSCL 0 400 kHz Hold Time Repeated START Condition, tHDSTA 0.6 μs Low Period of SCL Clock, tLOW 1.3 μs High Period of SCL Clock, tHIGH 0.6 μs Setup Time Repeated START Condition, tSUSTA 0.6 μs Data Hold Time, tHDDAT 0(2) 0.9(3) μs Data Setup Time, tSUDAT 100(4) ns Rise Time for Both SDA and SDL, tR 20 + 0.2CB (5) 300 ns Fall Time for Both SDA and SDL, tF 20 + 0.2CB (5) 300 ns Setup Time for STOP Condition, tSUSTO 0.6 μs Bus Free Time Between START and STOP, tBUF 1.3 μs Spike Pulse Width Suppressed by Input Filter, tSP 0 50 ns Capacitive Load for Each Bus Line, CB 400 pF Noise Margin at Low Level (including hysteresis), VNL 0.1 נ VIO V Noise Margin at High Level (including hysteresis), VNH 0.2 נ VIO V (1) All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of the Electrical Characteristics: General, SRC, DIR, and DIT table. (2) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH minimum input level) to bridge the undefined region of the falling edge of SCL. (3) The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal. (4) A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement that tSUDAT be 250ns minimum must then be met. For the SRC4382, this is automatically the case, since the device does not stretch the Low period of the SCL signal. (5) CB is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are allowed. Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): SRC4382 |
Similar Part No. - SRC4382_14 |
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