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L1DMPPA16 Datasheet(PDF) 2 Page - Texas Instruments |
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L1DMPPA16 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 222 page  OMAP-L137 SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014 www.ti.com • Two Master and Slave Inter-Integrated Circuit (I2C • 10/100 Mbps Ethernet MAC (EMAC): Bus™) – IEEE 802.3 Compliant (3.3-V I/O Only) • One Host-Port Interface (HPI) with 16-Bit-Wide – RMII Media-Independent Interface Muxed Address/Data Bus for High Bandwidth – Management Data I/O (MDIO) Module • Programmable Real-Time Unit Subsystem • Real-Time Clock with 32-kHz Oscillator and (PRUSS) Separate Power Rail – Two Independent Programmable Realtime Unit • One 64-Bit General-Purpose Timer (Configurable (PRU) Cores as Two 32-Bit Timers) • 32-Bit Load and Store RISC Architecture • One 64-Bit General-Purpose Watchdog Timer • 4KB of Instruction RAM per Core (Configurable as Two 32-Bit General-Purpose Timers) • 512 Bytes of Data RAM per Core • Three Enhanced Pulse Width Modulators • PRUSS can be Disabled via Software to (eHRPWMs): Save Power – Dedicated 16-Bit Time-Base Counter with – Standard Power-Management Mechanism Period and Frequency Control • Clock Gating – 6 Single Edge, 6 Dual Edge Symmetric, or 3 • Entire Subsystem Under a Single PSC Clock Dual Edge Asymmetric Outputs Gating Domain – Dead-Band Generation – Dedicated Interrupt Controller – PWM Chopping by High-Frequency Carrier – Dedicated Switched Central Resource – Trip Zone Input • USB 1.1 OHCI (Host) with Integrated PHY (USB1) • Three 32-Bit Enhanced Capture (eCAP) Modules: • USB 2.0 OTG Port with Integrated PHY (USB0) – Configurable as 3 Capture Inputs or 3 Auxiliary – USB 2.0 High- and Full-Speed Client Pulse Width Modulator (APWM) Outputs – USB 2.0 High-, Full-, and Low-Speed Host – Single-Shot Capture of up to Four Event Time- – End Point 0 (Control) Stamps – End Points 1,2,3,4 (Control, Bulk, Interrupt or • Two 32-Bit Enhanced Quadrature Encoder Pulse ISOC) RX and TX (eQEP) Modules • Three Multichannel Audio Serial Ports (McASPs): • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) – Six Clock Zones and 28 Serial Data Pins [ZKB Suffix], 1.0-mm Ball Pitch – Supports TDM, I2S, and Similar Formats • Commercial, Industrial, Extended, or Automotive – DIT-Capable (McASP2) Temperature – FIFO Buffers for Transmit and Receive 1.2 Applications • A/V Receivers • Home Theatre Systems • Automotive Amplifiers • Professional Audio • Soundbars • Network Streaming Audio 1.3 Description The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs. The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. 2 OMAP-L137 Low-Power Applications Processor Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP-L137 |
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Similar Description - L1DMPPA16 |
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