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S25FL512SAGMFI010 Datasheet(PDF) 8 Page - SPANSION |
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S25FL512SAGMFI010 Datasheet(HTML) 8 Page - SPANSION |
8 / 140 page 8 S25FL512S S25FL512S_00_07 January 8, 2014 Da ta Sh e e t Figure 10.12 Write Registers (WRR 01h) Command Sequence – 16 data bits . . . . . . . . . . . . . . . . . . . . . 82 Figure 10.13 Write Enable (WREN 06h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 10.14 Write Disable (WRDI 04h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 10.15 Clear Status Register (CLSR 30h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 10.16 AutoBoot Sequence (CR1[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 10.17 AutoBoot Sequence (CR1[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 10.18 AutoBoot Register Read (ABRD 14h) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 10.19 AutoBoot Register Write (ABWR) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 10.20 Program NVDLR (PNVDLR 43h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 10.21 Write VDLR (WVDLR 4Ah) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 10.22 DLP Read (DLPRD 41h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 10.23 Read Command Sequence (READ 03h or 13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 10.24 Fast Read (FAST_READ 0Bh or 0Ch) Command Sequence with Read Latency . . . . . . . . . 90 Figure 10.25 Fast Read Command (FAST_READ 0Bh or 0Ch) Sequence without Read Latency . . . . . . 91 Figure 10.26 Dual Output Read Command Sequence (3-Byte Address, 3Bh [ExtAdd=0], LC=10b). . . . . 91 Figure 10.27 Dual Output Read Command Sequence (4-Byte Address, 3Ch or 3Bh [ExtAdd=1, LC=10b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Figure 10.28 Dual Output Read Command Sequence (4-Byte Address, 3Ch or 3Bh [ExtAdd=1, LC=11b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 10.29 Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence with Read Latency . . . 93 Figure 10.30 Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence without Read Latency 93 Figure 10.31 Dual I/O Read Command Sequence (3-Byte Address, BBh [ExtAdd=0], HPLC=00b) . . . . . 94 Figure 10.32 Dual I/O Read Command Sequence (4-Byte Address, BBh [ExtAdd=1], HPLC=10b) . . . . . 95 Figure 10.33 Dual I/O Read Command Sequence (4-Byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Figure 10.34 Continuous Dual I/O Read Command Sequence (4-Byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 10.35 Quad I/O Read Command Sequence (3-Byte Address, EBh [ExtAdd=0], LC=00b) . . . . . . . 96 Figure 10.36 Continuous Quad I/O Read Command Sequence (3-Byte Address), LC=00b . . . . . . . . . . . 97 Figure 10.37 Quad I/O Read Command Sequence (4-Byte Address, ECh or EBh [ExtAdd=1], LC=00b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Figure 10.38 Continuous Quad I/O Read Command Sequence (4-Byte Address), LC=00b . . . . . . . . . . . 97 Figure 10.39 DDR Fast Read Initial Access (3-Byte Address, 0Dh [ExtAdd=0, EHPLC=11b]) . . . . . . . . . 99 Figure 10.40 Continuous DDR Fast Read Subsequent Access (3-Byte Address [ExtAdd=0, EHPLC=11b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Figure 10.41 DDR Fast Read Initial Access (4-Byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b). . . . 99 Figure 10.42 Continuous DDR Fast Read Subsequent Access (4-Byte Address [ExtAdd=1], EHPLC=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Figure 10.43 DDR Fast Read Subsequent Access (4-Byte Address, HPLC=01b) . . . . . . . . . . . . . . . . . . 100 Figure 10.44 DDR Dual I/O Read Initial Access (4-Byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b) . . . . . . . . . . . . . . . . . . . . . . . . . .101 Figure 10.45 Continuous DDR Dual I/O Read Subsequent Access (4-Byte Address, EHPLC= 01b) . . . 101 Figure 10.46 DDR Dual I/O Read (4-Byte Address, BEh or BDh [ExtAdd=1], HPLC=00b) . . . . . . . . . . . 102 Figure 10.47 DDR Quad I/O Read Initial Access (3-Byte Address, EDh [ExtAdd=0], HPLC=11b). . . . . . 103 Figure 10.48 Continuous DDR Quad I/O Read Subsequent Access (3-Byte Address,HPLC=11b) . . . . . 104 Figure 10.49 DDR Quad I/O Read Initial Access (4-Byte Address, EEh or EDh [ExtAdd=1], EHPLC=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Figure 10.50 Continuous DDR Quad I/O Read Subsequent Access (4-Byte Address, EHPLC=01b) . . . 104 Figure 10.51 Page Program (PP 02h or 4PP 12h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 10.52 Quad 512-byte Page Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 10.53 Program Suspend (PGSP 85h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 10.54 10.55 Program Resume (PGRS 8Ah) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 10.55 Sector Erase (SE D8h or 4SE DCh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 10.56 Bulk Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 10.57 Erase Suspend (ERSP 75h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 10.58 Erase Resume (ERRS 7Ah) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 |
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